From: Tom Rini Date: Mon, 17 Feb 2014 19:22:02 +0000 (-0500) Subject: Merge branch 'master' of git://git.denx.de/u-boot-arm X-Git-Tag: v2014.04-rc1~77 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c4d376fd1c2bce8d64cec0431dd3f24957b6dec4;hp=5e77a745b24d9b98aa635293972f04fd6f0c6b38;p=kernel%2Fu-boot.git Merge branch 'master' of git://git.denx.de/u-boot-arm --- diff --git a/MAKEALL b/MAKEALL index 562071a..54b0d89 100755 --- a/MAKEALL +++ b/MAKEALL @@ -529,6 +529,12 @@ LIST_sparc="$(targets_by_arch sparc)" LIST_nds32="$(targets_by_arch nds32)" +######################################################################### +## ARC Systems +######################################################################### + +LIST_arc="$(targets_by_arch arc)" + #----------------------------------------------------------------------- get_target_location() { diff --git a/README b/README index 176de61..fe48ccd 100644 --- a/README +++ b/README @@ -472,6 +472,12 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details @@ -896,6 +902,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... diff --git a/arch/arc/config.mk b/arch/arc/config.mk new file mode 100644 index 0000000..76f4f7c --- /dev/null +++ b/arch/arc/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SYS_BIG_ENDIAN +CONFIG_SYS_LITTLE_ENDIAN = 1 +endif + +ifdef CONFIG_SYS_LITTLE_ENDIAN +CROSS_COMPILE ?= arc-buildroot-linux-uclibc- +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +CROSS_COMPILE ?= arceb-buildroot-linux-uclibc- +PLATFORM_LDFLAGS += -EB +endif + +PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2 + +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds + +# Needed for relocation +LDFLAGS_FINAL += -pie + +# Load address for standalone apps +CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 + +# Support generic board on ARC +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile new file mode 100644 index 0000000..cdc5002 --- /dev/null +++ b/arch/arc/cpu/arc700/Makefile @@ -0,0 +1,13 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y += start.o + +obj-y += cache.o +obj-y += cpu.o +obj-y += interrupts.o +obj-y += reset.o +obj-y += timer.o diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c new file mode 100644 index 0000000..39d522d --- /dev/null +++ b/arch/arc/cpu/arc700/cache.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* Bit values in IC_CTRL */ +#define IC_CTRL_CACHE_DISABLE (1 << 0) + +/* Bit values in DC_CTRL */ +#define DC_CTRL_CACHE_DISABLE (1 << 0) +#define DC_CTRL_INV_MODE_FLUSH (1 << 6) +#define DC_CTRL_FLUSH_STATUS (1 << 8) + +int icache_status(void) +{ + return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) != + IC_CTRL_CACHE_DISABLE; +} + +void icache_enable(void) +{ + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & + ~IC_CTRL_CACHE_DISABLE); +} + +void icache_disable(void) +{ + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); +} + +void invalidate_icache_all(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ + write_aux_reg(ARC_AUX_IC_IVIC, 1); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} + +int dcache_status(void) +{ + return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) != + DC_CTRL_CACHE_DISABLE; +} + +void dcache_enable(void) +{ + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & + ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); +} + +void dcache_disable(void) +{ + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | + DC_CTRL_CACHE_DISABLE); +} + +void flush_dcache_all(void) +{ + /* Do flush of entire cache */ + write_aux_reg(ARC_AUX_DC_FLSH, 1); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +static void dcache_flush_line(unsigned addr) +{ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_FLDL, addr); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; + +#ifndef CONFIG_SYS_ICACHE_OFF + /* + * Invalidate I$ for addresses range just flushed from D$. + * If we try to execute data flushed above it will be valid/correct + */ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_IC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_IC_IVIL, addr); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} +#endif /* CONFIG_SYS_DCACHE_OFF */ + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) + dcache_flush_line(addr); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_IVDL, addr); + } +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_all(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */ + write_aux_reg(ARC_AUX_DC_IVDC, 1); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk new file mode 100644 index 0000000..3206ff4 --- /dev/null +++ b/arch/arc/cpu/arc700/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -mA7 diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c new file mode 100644 index 0000000..50634b8 --- /dev/null +++ b/arch/arc/cpu/arc700/cpu.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SYS_ICACHE_OFF + icache_disable(); +#else + icache_enable(); + invalidate_icache_all(); +#endif + + flush_dcache_all(); +#ifdef CONFIG_SYS_DCACHE_OFF + dcache_disable(); +#else + dcache_enable(); +#endif + timer_init(); + +/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */ + if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00) + gd->arch.running_on_hw = 0; + else + gd->arch.running_on_hw = 1; + + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int arch_early_init_r(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c new file mode 100644 index 0000000..d93a6eb --- /dev/null +++ b/arch/arc/cpu/arc700/interrupts.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* Bit values in STATUS32 */ +#define E1_MASK (1 << 1) /* Level 1 interrupts enable */ +#define E2_MASK (1 << 2) /* Level 2 interrupts enable */ + +int interrupt_init(void) +{ + return 0; +} + +/* + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts(void) +{ + int status = read_aux_reg(ARC_AUX_STATUS32); + int state = (status | E1_MASK | E2_MASK) ? 1 : 0; + + status &= ~(E1_MASK | E2_MASK); + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); + return state; +} + +void enable_interrupts(void) +{ + unsigned int status = read_aux_reg(ARC_AUX_STATUS32); + + status |= E1_MASK | E2_MASK; + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); +} + +static void print_reg_file(long *reg_rev, int start_num) +{ + unsigned int i; + + /* Print 3 registers per line */ + for (i = start_num; i < start_num + 25; i++) { + printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev); + if (((i + 1) % 3) == 0) + printf("\n"); + + /* Because pt_regs has registers reversed */ + reg_rev--; + } + + /* Add new-line if none was inserted in the end of loop above */ + if (((i + 1) % 3) != 0) + printf("\n"); +} + +void show_regs(struct pt_regs *regs) +{ + printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n", + regs->ret, regs->blink, regs->status32); + printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25); + printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta, + regs->sp, regs->fp); + printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start, + regs->lp_end, regs->lp_count); + + print_reg_file(&(regs->r0), 0); +} + +void bad_mode(struct pt_regs *regs) +{ + if (regs) + show_regs(regs); + + panic("Resetting CPU ...\n"); +} + +void do_memory_error(unsigned long address, struct pt_regs *regs) +{ + printf("Memory error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_instruction_error(unsigned long address, struct pt_regs *regs) +{ + printf("Instruction error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_machine_check_fault(unsigned long address, struct pt_regs *regs) +{ + printf("Machine check exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_interrupt_handler(void) +{ + printf("Interrupt fired\n"); + bad_mode(0); +} + +void do_itlb_miss(struct pt_regs *regs) +{ + printf("I TLB miss exception\n"); + bad_mode(regs); +} + +void do_dtlb_miss(struct pt_regs *regs) +{ + printf("D TLB miss exception\n"); + bad_mode(regs); +} + +void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs) +{ + printf("TLB protection violation or misaligned access @ 0x%lx\n", + address); + bad_mode(regs); +} + +void do_privilege_violation(struct pt_regs *regs) +{ + printf("Privilege violation exception\n"); + bad_mode(regs); +} + +void do_trap(struct pt_regs *regs) +{ + printf("Trap exception\n"); + bad_mode(regs); +} + +void do_extension(struct pt_regs *regs) +{ + printf("Extension instruction exception\n"); + bad_mode(regs); +} diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c new file mode 100644 index 0000000..98ebf1d --- /dev/null +++ b/arch/arc/cpu/arc700/reset.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("Put your restart handler here\n"); + +#ifdef DEBUG + /* Stop debug session here */ + __asm__("brk"); +#endif + return 0; +} diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S new file mode 100644 index 0000000..563513b --- /dev/null +++ b/arch/arc/cpu/arc700/start.S @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Note on the LD/ST addressing modes with address register write-back + * + * LD.a same as LD.aw + * + * LD.a reg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +.macro PUSH reg + st.a \reg, [%sp, -4] +.endm + +.macro PUSHAX aux + lr %r9, [\aux] + PUSH %r9 +.endm + +.macro SAVE_R1_TO_R24 + PUSH %r1 + PUSH %r2 + PUSH %r3 + PUSH %r4 + PUSH %r5 + PUSH %r6 + PUSH %r7 + PUSH %r8 + PUSH %r9 + PUSH %r10 + PUSH %r11 + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + PUSH %r16 + PUSH %r17 + PUSH %r18 + PUSH %r19 + PUSH %r20 + PUSH %r21 + PUSH %r22 + PUSH %r23 + PUSH %r24 +.endm + +.macro SAVE_ALL_SYS + + st %r0, [%sp] + lr %r0, [%ecr] + st %r0, [%sp, 8] /* ECR */ + st %sp, [%sp, 4] + + SAVE_R1_TO_R24 + PUSH %r25 + PUSH %gp + PUSH %fp + PUSH %blink + PUSHAX %eret + PUSHAX %erstatus + PUSH %lp_count + PUSHAX %lp_end + PUSHAX %lp_start + PUSHAX %erbta +.endm + +.align 4 +.globl _start +_start: + /* Critical system events */ + j reset /* 0 - 0x000 */ + j memory_error /* 1 - 0x008 */ + j instruction_error /* 2 - 0x010 */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr + /* Exceptions */ + j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ + j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ + j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ + j EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ + j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ + j EV_Trap /* 0x128, Trap exception (0x25) */ + j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ + +memory_error: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_memory_error + +instruction_error: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_instruction_error + +interrupt_handler: + /* Todo - save and restore CPU context when interrupts will be in use */ + bl do_interrupt_handler + rtie + +EV_MachineCheck: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_machine_check_fault + +EV_TLBMissI: + SAVE_ALL_SYS + mov %r0, %sp + j do_itlb_miss + +EV_TLBMissD: + SAVE_ALL_SYS + mov %r0, %sp + j do_dtlb_miss + +EV_TLBProtV: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_tlb_prot_violation + +EV_PrivilegeV: + SAVE_ALL_SYS + mov %r0, %sp + j do_privilege_violation + +EV_Trap: + SAVE_ALL_SYS + mov %r0, %sp + j do_trap + +EV_Extension: + SAVE_ALL_SYS + mov %r0, %sp + j do_extension + + +reset: + /* Setup interrupt vector base that matches "__text_start" */ + sr __text_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack pointer */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Clear bss */ + mov %r0, __bss_start + mov %r1, __bss_end + +clear_bss: + st.ab 0, [%r0, 4] + brlt %r0, %r1, clear_bss + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r0 = start_addr_sp + * r1 = new__gd + * r2 = relocaddr + */ +.align 4 +.globl relocate_code +relocate_code: + /* + * r0-r12 might be clobbered by C functions + * so we use r13-r16 for storage here + */ + mov %r13, %r0 /* save addr_sp */ + mov %r14, %r1 /* save addr of gd */ + mov %r15, %r2 /* save addr of destination */ + + mov %r16, %r2 /* %r9 - relocation offset */ + sub %r16, %r16, __image_copy_start + +/* Set up the stack */ +stack_setup: + mov %sp, %r13 + mov %fp, %sp + +/* Check if monitor is loaded right in place for relocation */ + mov %r0, __image_copy_start + cmp %r0, %r15 /* skip relocation if code loaded */ + bz do_board_init_r /* in target location already */ + +/* Copy data (__image_copy_start - __image_copy_end) to new location */ + mov %r1, %r15 + mov %r2, __image_copy_end + sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ + asr %r2, %r2, 2 /* r3 <- amount of words to copy */ + mov %lp_count, %r2 + lp copy_end + ld.ab %r2,[%r0,4] + st.ab %r2,[%r1,4] +copy_end: + +/* Fix relocations related issues */ + bl do_elf_reloc_fixups +#ifndef CONFIG_SYS_ICACHE_OFF + bl invalidate_icache_all +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + bl flush_dcache_all +#endif + +/* Update position of intterupt vector table */ + lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ + add %r0, %r0, %r16 /* Update address */ + sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ + +do_board_init_r: +/* Prepare for exection of "board_init_r" in relocated monitor */ + mov %r2, board_init_r /* old address of "board_init_r()" */ + add %r2, %r2, %r16 /* new address of "board_init_r()" */ + mov %r0, %r14 /* 1-st parameter: gd_t */ + mov %r1, %r15 /* 2-nd parameter: dest_addr */ + j [%r2] diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c new file mode 100644 index 0000000..a0acbbc --- /dev/null +++ b/arch/arc/cpu/arc700/timer.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */ + +int timer_init(void) +{ + write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); + /* Set max value for counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); + /* Set initial count value and restart counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_CNT, 0); + return 0; +} + +unsigned long timer_read_counter(void) +{ + return read_aux_reg(ARC_AUX_TIMER0_CNT); +} diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds new file mode 100644 index 0000000..2d01b21 --- /dev/null +++ b/arch/arc/cpu/arc700/u-boot.lds @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") +OUTPUT_ARCH(arc) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : { + *(.__text_start) + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .text_end : + { + *(.__text_end) + } + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rel_dyn_start : { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela.dyn) + } + + .rel_dyn_end : { + *(.__rel_dyn_end) + } + + . = ALIGN(4); + .bss_start : { + *(.__bss_start); + } + + .bss : { + *(.bss*) + } + + .bss_end : { + *(.__bss_end); + } + + . = ALIGN(4); + .image_copy_end : { + *(.__image_copy_end) + *(.__init_end) + } +} diff --git a/arch/arc/include/asm/arch-arc700/hardware.h b/arch/arc/include/asm/arch-arc700/hardware.h new file mode 100644 index 0000000..8ec13a8 --- /dev/null +++ b/arch/arc/include/asm/arch-arc700/hardware.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file is only required to allow compilation of "designware_i2c" driver. + * Which explicitly includes . + */ diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h new file mode 100644 index 0000000..5d48d11 --- /dev/null +++ b/arch/arc/include/asm/arcregs.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_ARCREGS_H +#define _ASM_ARC_ARCREGS_H + +/* + * ARC architecture has additional address space - auxiliary registers. + * These registers are mostly used for configuration purposes. + * These registers are not memory mapped and special commands are used for + * access: "lr"/"sr". + */ + +#define ARC_AUX_IDENTITY 0x04 +#define ARC_AUX_STATUS32 0x0a + +/* Instruction cache related auxiliary registers */ +#define ARC_AUX_IC_IVIC 0x10 +#define ARC_AUX_IC_CTRL 0x11 +#define ARC_AUX_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_IC_PTAG 0x1E +#endif + +/* Timer related auxiliary registers */ +#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ +#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ +#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ + +#define ARC_AUX_INTR_VEC_BASE 0x25 + +/* Data cache related auxiliary registers */ +#define ARC_AUX_DC_IVDC 0x47 +#define ARC_AUX_DC_CTRL 0x48 + +#define ARC_AUX_DC_IVDL 0x4A +#define ARC_AUX_DC_FLSH 0x4B +#define ARC_AUX_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_DC_PTAG 0x5C +#endif + +#ifndef __ASSEMBLY__ +/* Accessors for auxiliary registers */ +#define read_aux_reg(reg) __builtin_arc_lr(reg) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(reg_immed, val) \ + __builtin_arc_sr((unsigned int)val, reg_immed) +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h new file mode 100644 index 0000000..85721aa --- /dev/null +++ b/arch/arc/include/asm/bitops.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BITOPS_H +#define __ASM_ARC_BITOPS_H + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __ASM_ARC_BITOPS_H */ diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h new file mode 100644 index 0000000..2fa9776 --- /dev/null +++ b/arch/arc/include/asm/byteorder.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BYTEORDER_H +#define __ASM_ARC_BYTEORDER_H + +#include + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) + #define __BYTEORDER_HAS_U64__ + #define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ + #include +#else + #include +#endif /* CONFIG_SYS_BIG_ENDIAN */ + +#endif /* ASM_ARC_BYTEORDER_H */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h new file mode 100644 index 0000000..16e7568 --- /dev/null +++ b/arch/arc/include/asm/cache.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CACHE_H +#define __ASM_ARC_CACHE_H + +#include + +/* + * The current upper bound for ARC L1 data cache line sizes is 128 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 128 +#endif + +#endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h new file mode 100644 index 0000000..5761def --- /dev/null +++ b/arch/arc/include/asm/config.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CONFIG_H_ +#define __ASM_ARC_CONFIG_H_ + +#define CONFIG_LMB + +#endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h new file mode 100644 index 0000000..4c82b50 --- /dev/null +++ b/arch/arc/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h new file mode 100644 index 0000000..d644e80 --- /dev/null +++ b/arch/arc/include/asm/global_data.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_GLOBAL_DATA_H +#define __ASM_ARC_GLOBAL_DATA_H + +/* Architecture-specific global data */ +struct arch_global_data { + int running_on_hw; +}; + +#include + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25") + +#endif /* __ASM_ARC_GLOBAL_DATA_H */ diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h new file mode 100644 index 0000000..24b7337 --- /dev/null +++ b/arch/arc/include/asm/io.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_IO_H +#define __ASM_ARC_IO_H + +#include +#include + +static inline void sync(void) +{ + /* Not yet implemented */ +} + +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 b; + + __asm__ __volatile__("ldb%U1 %0, %1\n" + : "=r" (b) + : "m" (*(volatile u8 __force *)addr) + : "memory"); + return b; +} + +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 s; + + __asm__ __volatile__("ldw%U1 %0, %1\n" + : "=r" (s) + : "m" (*(volatile u16 __force *)addr) + : "memory"); + return s; +} + +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 w; + + __asm__ __volatile__("ld%U1 %0, %1\n" + : "=r" (w) + : "m" (*(volatile u32 __force *)addr) + : "memory"); + return w; +} + +#define readb __raw_readb + +static inline u16 readw(const volatile void __iomem *addr) +{ + return __le16_to_cpu(__raw_readw(addr)); +} + +static inline u32 readl(const volatile void __iomem *addr) +{ + return __le32_to_cpu(__raw_readl(addr)); +} + +static inline void __raw_writeb(u8 b, volatile void __iomem *addr) +{ + __asm__ __volatile__("stb%U1 %0, %1\n" + : + : "r" (b), "m" (*(volatile u8 __force *)addr) + : "memory"); +} + +static inline void __raw_writew(u16 s, volatile void __iomem *addr) +{ + __asm__ __volatile__("stw%U1 %0, %1\n" + : + : "r" (s), "m" (*(volatile u16 __force *)addr) + : "memory"); +} + +static inline void __raw_writel(u32 w, volatile void __iomem *addr) +{ + __asm__ __volatile__("st%U1 %0, %1\n" + : + : "r" (w), "m" (*(volatile u32 __force *)addr) + : "memory"); +} + +#define writeb __raw_writeb +#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr) +#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr) + +static inline int __raw_readsb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stb.ab r8, [r1, 1]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_readsw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stw.ab r8, [r1, 2]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_readsl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab r8, [r1, 4]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +static inline int __raw_writesb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_writesw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_writesl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#endif /* __ASM_ARC_IO_H */ diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h new file mode 100644 index 0000000..20415f0 --- /dev/null +++ b/arch/arc/include/asm/posix_types.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_POSIX_TYPES_H +#define __ASM_ARC_POSIX_TYPES_H + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +#endif /* __ASM_ARC_POSIX_TYPES_H */ diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h new file mode 100644 index 0000000..8f73b31 --- /dev/null +++ b/arch/arc/include/asm/ptrace.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_PTRACE_H +#define __ASM_ARC_PTRACE_H + +struct pt_regs { + long bta; + long lp_start; + long lp_end; + long lp_count; + long status32; + long ret; + long blink; + long fp; + long r26; /* gp */ + long r25; + long r24; + long r23; + long r22; + long r21; + long r20; + long r19; + long r18; + long r17; + long r16; + long r15; + long r14; + long r13; + long r12; + long r11; + long r10; + long r9; + long r8; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long sp; + long ecr; +}; + +#endif /* __ASM_ARC_PTRACE_H */ diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h new file mode 100644 index 0000000..18484a1 --- /dev/null +++ b/arch/arc/include/asm/sections.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_SECTIONS_H +#define __ASM_ARC_SECTIONS_H + +#include + +extern ulong __text_end; + +#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h new file mode 100644 index 0000000..909129c --- /dev/null +++ b/arch/arc/include/asm/string.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_STRING_H +#define __ASM_ARC_STRING_H + +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_STRCHR +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRLEN + +extern void *memset(void *ptr, int, __kernel_size_t); +extern void *memcpy(void *, const void *, __kernel_size_t); +extern void memzero(void *ptr, __kernel_size_t n); +extern int memcmp(const void *, const void *, __kernel_size_t); +extern char *strchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern int strcmp(const char *cs, const char *ct); +extern __kernel_size_t strlen(const char *); + +#endif /* __ASM_ARC_STRING_H */ diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h new file mode 100644 index 0000000..24eeb76 --- /dev/null +++ b/arch/arc/include/asm/types.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_TYPES_H +#define __ASM_ARC_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __ASM_ARC_TYPES_H */ diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h new file mode 100644 index 0000000..0c0e8e6 --- /dev/null +++ b/arch/arc/include/asm/u-boot-arc.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_ARC_H__ +#define __ASM_ARC_U_BOOT_ARC_H__ + +int arch_early_init_r(void); + +#endif /* __ASM_ARC_U_BOOT_ARC_H__ */ diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h new file mode 100644 index 0000000..e354edf --- /dev/null +++ b/arch/arc/include/asm/u-boot.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_H__ +#define __ASM_ARC_U_BOOT_H__ + +#include + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_ARC + +#endif /* __ASM_ARC_U_BOOT_H__ */ diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h new file mode 100644 index 0000000..6cecbbb --- /dev/null +++ b/arch/arc/include/asm/unaligned.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile new file mode 100644 index 0000000..7675f85 --- /dev/null +++ b/arch/arc/lib/Makefile @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sections.o +obj-y += relocate.o +obj-y += strchr-700.o +obj-y += strcmp.o +obj-y += strcpy-700.o +obj-y += strlen.o +obj-y += memcmp.o +obj-y += memcpy-700.o +obj-y += memset.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c new file mode 100644 index 0000000..d185a50 --- /dev/null +++ b/arch/arc/lib/bootm.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); +} + +static int cleanup_before_linux(void) +{ + disable_interrupts(); + flush_dcache_all(); + invalidate_icache_all(); + + return 0; +} + +/* Subcommand: PREP */ +static void boot_prep_linux(bootm_headers_t *images) +{ + if (image_setup_linux(images)) + hang(); +} + +/* Subcommand: GO */ +static void boot_jump_linux(bootm_headers_t *images, int flag) +{ + void (*kernel_entry)(int zero, int arch, uint params); + unsigned int r0, r2; + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel_entry = (void (*)(int, int, uint))images->ep; + + debug("## Transferring control to Linux (at address %08lx)...\n", + (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + printf("\nStarting kernel ...%s\n\n", fake ? + "(fake run for tracing)" : ""); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + + cleanup_before_linux(); + + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + r0 = 2; + r2 = (unsigned int)images->ft_addr; + } else { + r0 = 1; + r2 = (unsigned int)getenv("bootargs"); + } + + if (!fake) + kernel_entry(r0, 0, r2); +} + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + /* No need for those on ARC */ + if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE)) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + boot_jump_linux(images, flag); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images, flag); + return 0; +} diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S new file mode 100644 index 0000000..fa5aac5 --- /dev/null +++ b/arch/arc/lib/memcmp.S @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __LITTLE_ENDIAN__ +#define WORD2 r2 +#define SHIFT r3 +#else /* __BIG_ENDIAN__ */ +#define WORD2 r3 +#define SHIFT r2 +#endif /* _ENDIAN__ */ + +.global memcmp +.align 4 +memcmp: + or %r12, %r0, %r1 + asl_s %r12, %r12, 30 + sub %r3, %r2, 1 + brls %r2, %r12, .Lbytewise + ld %r4, [%r0, 0] + ld %r5, [%r1, 0] + lsr.f %lp_count, %r3, 3 + lpne .Loop_end + ld_s WORD2, [%r0, 4] + ld_s %r12, [%r1, 4] + brne %r4, %r5, .Leven + ld.a %r4, [%r0, 8] + ld.a %r5, [%r1, 8] + brne WORD2, %r12, .Lodd +.Loop_end: + asl_s SHIFT, SHIFT, 3 + bhs_s .Last_cmp + brne %r4, %r5, .Leven + ld %r4, [%r0, 4] + ld %r5, [%r1, 4] +#ifdef __LITTLE_ENDIAN__ + nop_s + /* one more load latency cycle */ +.Last_cmp: + xor %r0, %r4, %r5 + bset %r0, %r0, SHIFT + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + b.d .Leven_cmp + and %r1, %r1, 24 +.Leven: + xor %r0, %r4, %r5 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 +.Leven_cmp: + asl %r2, %r4, %r1 + asl %r12, %r5, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 + .balign 4 +.Lodd: + xor %r0, WORD2, %r12 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 + asl_s %r2, %r2, %r1 + asl_s %r12, %r12, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 +#else /* __BIG_ENDIAN__ */ +.Last_cmp: + neg_s SHIFT, SHIFT + lsr %r4, %r4, SHIFT + lsr %r5, %r5, SHIFT + /* slow track insn */ +.Leven: + sub.f %r0, %r4, %r5 + mov.ne %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +.Lodd: + cmp_s WORD2, %r12 + + mov_s %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +#endif /* _ENDIAN__ */ + .balign 4 +.Lbytewise: + breq %r2, 0, .Lnil + ldb %r4, [%r0, 0] + ldb %r5, [%r1, 0] + lsr.f %lp_count, %r3 + lpne .Lbyte_end + ldb_s %r3, [%r0, 1] + ldb %r12, [%r1, 1] + brne %r4, %r5, .Lbyte_even + ldb.a %r4, [%r0, 2] + ldb.a %r5, [%r1, 2] + brne %r3, %r12, .Lbyte_odd +.Lbyte_end: + bcc .Lbyte_even + brne %r4, %r5, .Lbyte_even + ldb_s %r3, [%r0, 1] + ldb_s %r12, [%r1, 1] +.Lbyte_odd: + j_s.d [%blink] + sub %r0, %r3, %r12 +.Lbyte_even: + j_s.d [%blink] + sub %r0, %r4, %r5 +.Lnil: + j_s.d [%blink] + mov %r0, 0 diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S new file mode 100644 index 0000000..51dd73a --- /dev/null +++ b/arch/arc/lib/memcpy-700.S @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global memcpy +.align 4 +memcpy: + or %r3, %r0, %r1 + asl_s %r3, %r3, 30 + mov_s %r5, %r0 + brls.d %r2, %r3, .Lcopy_bytewise + sub.f %r3, %r2, 1 + ld_s %r12, [%r1, 0] + asr.f %lp_count, %r3, 3 + bbit0.d %r3, 2, .Lnox4 + bmsk_s %r2, %r2, 1 + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 4] +.Lnox4: + lppnz .Lendloop + ld_s %r3, [%r1, 4] + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 8] + st.ab %r3, [%r5, 4] +.Lendloop: + breq %r2, 0, .Last_store + ld %r3, [%r5, 0] +#ifdef __LITTLE_ENDIAN__ + add3 %r2, -1, %r2 + /* uses long immediate */ + xor_s %r12, %r12, %r3 + bmsk %r12, %r12, %r2 + xor_s %r12, %r12, %r3 +#else /* __BIG_ENDIAN__ */ + sub3 %r2, 31, %r2 + /* uses long immediate */ + xor_s %r3, %r3, %r12 + bmsk %r3, %r3, %r2 + xor_s %r12, %r12, %r3 +#endif /* _ENDIAN__ */ +.Last_store: + j_s.d [%blink] + st %r12, [%r5, 0] + + .balign 4 +.Lcopy_bytewise: + jcs [%blink] + ldb_s %r12, [%r1, 0] + lsr.f %lp_count, %r3 + bhs_s .Lnox1 + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 1] +.Lnox1: + lppnz .Lendbloop + ldb_s %r3, [%r1, 1] + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 2] + stb.ab %r3, [%r5, 1] +.Lendbloop: + j_s.d [%blink] + stb %r12, [%r5, 0] diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S new file mode 100644 index 0000000..017e8af --- /dev/null +++ b/arch/arc/lib/memset.S @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ + +.global memset +.align 4 +memset: + mov_s %r4, %r0 + or %r12, %r0, %r2 + bmsk.f %r12, %r12, 1 + extb_s %r1, %r1 + asl %r3, %r1, 8 + beq.d .Laligned + or_s %r1, %r1, %r3 + brls %r2, SMALL, .Ltiny + add %r3, %r2, %r0 + stb %r1, [%r3, -1] + bclr_s %r3, %r3, 0 + stw %r1, [%r3, -2] + bmsk.f %r12, %r0, 1 + add_s %r2, %r2, %r12 + sub.ne %r2, %r2, 4 + stb.ab %r1, [%r4, 1] + and %r4, %r4, -2 + stw.ab %r1, [%r4, 2] + and %r4, %r4, -4 + + .balign 4 +.Laligned: + asl %r3, %r1, 16 + lsr.f %lp_count, %r2, 2 + or_s %r1, %r1, %r3 + lpne .Loop_end + st.ab %r1, [%r4, 4] +.Loop_end: + j_s [%blink] + + .balign 4 +.Ltiny: + mov.f %lp_count, %r2 + lpne .Ltiny_end + stb.ab %r1, [%r4, 1] +.Ltiny_end: + j_s [%blink] + +/* + * memzero: @r0 = mem, @r1 = size_t + * memset: @r0 = mem, @r1 = char, @r2 = size_t + */ + +.global memzero +.align 4 +memzero: + /* adjust bzero args to memset args */ + mov %r2, %r1 + mov %r1, 0 + /* tail call so need to tinker with blink */ + b memset diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c new file mode 100644 index 0000000..956aa14 --- /dev/null +++ b/arch/arc/lib/relocate.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Base functionality is taken from x86 version with added ARC-specifics + */ +int do_elf_reloc_fixups(void) +{ + Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); + Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + + Elf32_Addr *offset_ptr_rom, *last_offset = NULL; + Elf32_Addr *offset_ptr_ram; + + do { + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE && + offset_ptr_rom > last_offset) { + unsigned int val; + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* + * Use "memcpy" because target location might be + * 16-bit aligned on ARC so we may need to read + * byte-by-byte. On attempt to read entire word by + * CPU throws an exception + */ + memcpy(&val, offset_ptr_ram, sizeof(int)); + + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__text_end) + val = (val << 16) | (val >> 16); + + /* Check that the target points into .text */ + if (val >= CONFIG_SYS_TEXT_BASE && val <= + (unsigned int)&__bss_end) { + val += gd->reloc_off; + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__text_end) + val = (val << 16) | (val >> 16); + memcpy(offset_ptr_ram, &val, sizeof(int)); + } else { + debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n", + re_src, re_src->r_offset, offset_ptr_ram, + val, (unsigned int)&__bss_end); + } + } else { + debug(" %p: rom reloc %x, last %p\n", re_src, + re_src->r_offset, last_offset); + } + last_offset = offset_ptr_rom; + + } while (++re_src < re_end); + + return 0; +} diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c new file mode 100644 index 0000000..b0b46a4 --- /dev/null +++ b/arch/arc/lib/sections.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * For some reason linker sets linker-generated symbols to zero in PIE mode. + * A work-around is substitution of linker-generated symbols with + * compiler-generated symbols which are properly handled by linker in PAE mode. + */ + +char __bss_start[0] __attribute__((section(".__bss_start"))); +char __bss_end[0] __attribute__((section(".__bss_end"))); +char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); +char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); +char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); +char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __text_start[0] __attribute__((section(".__text_start"))); +char __text_end[0] __attribute__((section(".__text_end"))); +char __init_end[0] __attribute__((section(".__init_end"))); diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S new file mode 100644 index 0000000..55fcc9f --- /dev/null +++ b/arch/arc/lib/strchr-700.S @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * ARC700 has a relatively long pipeline and branch prediction, so we want + * to avoid branches that are hard to predict. On the other hand, the + * presence of the norm instruction makes it easier to operate on whole + * words branch-free. + */ + +.global strchr +.align 4 +strchr: + extb_s %r1, %r1 + asl %r5, %r1, 8 + bmsk %r2, %r0, 1 + or %r5, %r5, %r1 + mov_s %r3, 0x01010101 + breq.d %r2, %r0, .Laligned + asl %r4, %r5, 16 + sub_s %r0, %r0, %r2 + asl %r7, %r2, 3 + ld_s %r2, [%r0] +#ifdef __LITTLE_ENDIAN__ + asl %r7, %r3, %r7 +#else /* __BIG_ENDIAN__ */ + lsr %r7, %r3, %r7 +#endif /* _ENDIAN__ */ + or %r5, %r5, %r4 + ror %r4, %r3 + sub %r12, %r2, %r7 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0_ua + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 +#ifdef __LITTLE_ENDIAN__ + and %r7, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r7, 0, .Loop + /* Likewise this one */ + b .Lfound_char +#else /* __BIG_ENDIAN__ */ + and %r12, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r12, 0, .Loop + lsr_s %r12, %r12, 7 + bic %r2, %r7, %r6 + b.d .Lfound_char_b + and_s %r2, %r2, %r12 +#endif /* _ENDIAN__ */ + /* We require this code address to be unaligned for speed... */ +.Laligned: + ld_s %r2, [%r0] + or %r5, %r5, %r4 + ror %r4, %r3 + /* ... so that this code address is aligned, for itself and ... */ +.Loop: + sub %r12, %r2, %r3 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0 + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r3 + bic %r12, %r12, %r6 + and %r7, %r12, %r4 + breq %r7, 0, .Loop + /* + *... so that this branch is unaligned. + * Found searched-for character. + * r0 has already advanced to next word. + */ +#ifdef __LITTLE_ENDIAN__ + /* + * We only need the information about the first matching byte + * (i.e. the least significant matching byte) to be exact, + * hence there is no problem with carry effects. + */ +.Lfound_char: + sub %r3, %r7, 1 + bic %r3, %r3, %r7 + norm %r2, %r3 + sub_s %r0, %r0, 1 + asr_s %r2, %r2, 3 + j.d [%blink] + sub_s %r0, %r0, %r2 + + .balign 4 +.Lfound0_ua: + mov %r3, %r7 +.Lfound0: + sub %r3, %r6, %r3 + bic %r3, %r3, %r6 + and %r2, %r3, %r4 + or_s %r12, %r12, %r2 + sub_s %r3, %r12, 1 + bic_s %r3, %r3, %r12 + norm %r3, %r3 + add_s %r0, %r0, 3 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + sub_s %r0, %r0, %r12 + j_s.d [%blink] + mov.pl %r0, 0 +#else /* __BIG_ENDIAN__ */ +.Lfound_char: + lsr %r7, %r7, 7 + + bic %r2, %r7, %r6 +.Lfound_char_b: + norm %r2, %r2 + sub_s %r0, %r0, 4 + asr_s %r2, %r2, 3 + j.d [%blink] + add_s %r0, %r0, %r2 + +.Lfound0_ua: + mov_s %r3, %r7 +.Lfound0: + asl_s %r2, %r2, 7 + or %r7, %r6, %r4 + bic_s %r12, %r12, %r2 + sub %r2, %r7, %r3 + or %r2, %r2, %r6 + bic %r12, %r2, %r12 + bic.f %r3, %r4, %r12 + norm %r3, %r3 + + add.pl %r3, %r3, 1 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + add_s %r0, %r0, %r12 + j_s.d [%blink] + mov.mi %r0, 0 +#endif /* _ENDIAN__ */ diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S new file mode 100644 index 0000000..8cb7d2f --- /dev/null +++ b/arch/arc/lib/strcmp.S @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is optimized primarily for the ARC700. + * It would be possible to speed up the loops by one cycle / word + * respective one cycle / byte by forcing double source 1 alignment, unrolling + * by a factor of two, and speculatively loading the second word / byte of + * source 1; however, that would increase the overhead for loop setup / finish, + * and strcmp might often terminate early. + */ + +.global strcmp +.align 4 +strcmp: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne %r2, 0, .Lcharloop + mov_s %r12, 0x01010101 + ror %r5, %r12 +.Lwordloop: + ld.ab %r2, [%r0, 4] + ld.ab %r3, [%r1, 4] + nop_s + sub %r4, %r2, %r12 + bic %r4, %r4, %r2 + and %r4, %r4, %r5 + brne %r4, 0, .Lfound0 + breq %r2 ,%r3, .Lwordloop +#ifdef __LITTLE_ENDIAN__ + xor %r0, %r2, %r3 /* mask for difference */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 +#endif /* _ENDIAN__ */ + cmp_s %r2, %r3 + mov_s %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 + + .balign 4 +#ifdef __LITTLE_ENDIAN__ +.Lfound0: + xor %r0, %r2, %r3 /* mask for difference */ + or %r0, %r0, %r4 /* or in zero indicator */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 + sub.f %r0, %r2, %r3 + mov.hi %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#else /* __BIG_ENDIAN__ */ + /* + * The zero-detection above can mis-detect 0x01 bytes as zeroes + * because of carry-propagateion from a lower significant zero byte. + * We can compensate for this by checking that bit0 is zero. + * This compensation is not necessary in the step where we + * get a low estimate for r2, because in any affected bytes + * we already have 0x00 or 0x01, which will remain unchanged + * when bit 7 is cleared. + */ + .balign 4 +.Lfound0: + lsr %r0, %r4, 8 + lsr_s %r1, %r2 + bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */ + bic_s %r0, %r0, %r1 /* */ + or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */ + cmp_s %r3, %r2 /* ... be independent of trailing garbage */ + or_s %r2, %r2, %r0 /* likewise for r3 > r2 */ + bic_s %r3, %r3, %r0 + rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */ + cmp_s %r2, %r3 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#endif /* _ENDIAN__ */ + + .balign 4 +.Lcharloop: + ldb.ab %r2,[%r0,1] + ldb.ab %r3,[%r1,1] + nop_s + breq %r2, 0, .Lcmpend + breq %r2, %r3, .Lcharloop +.Lcmpend: + j_s.d [%blink] + sub %r0, %r2, %r3 diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S new file mode 100644 index 0000000..41bb53e --- /dev/null +++ b/arch/arc/lib/strcpy-700.S @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * If dst and src are 4 byte aligned, copy 8 bytes at a time. + * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get + * it 8 byte aligned. Thus, we can do a little read-ahead, without + * dereferencing a cache line that we should not touch. + * Note that short and long instructions have been scheduled to avoid + * branch stalls. + * The beq_s to r3z could be made unaligned & long to avoid a stall + * there, but it is not likely to be taken often, and it would also be likely + * to cost an unaligned mispredict at the next call. + */ + +.global strcpy +.align 4 +strcpy: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne.d %r2, 0, charloop + mov_s %r10, %r0 + ld_s %r3, [%r1, 0] + mov %r8, 0x01010101 + bbit0.d %r1, 2, loop_start + ror %r12, %r8 + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2,%r12 + bne r3z + mov_s %r4,%r3 + .balign 4 +loop: + ld.a %r3, [%r1, 4] + st.ab %r4, [%r10, 4] +loop_start: + ld.a %r4, [%r1, 4] + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2, %r12 + bne_s r3z + st.ab %r3, [%r10, 4] + sub %r2, %r4, %r8 + bic %r2, %r2, %r4 + tst %r2, %r12 + beq loop + mov_s %r3, %r4 +#ifdef __LITTLE_ENDIAN__ +r3z: bmsk.f %r1, %r3, 7 + lsr_s %r3, %r3, 8 +#else /* __BIG_ENDIAN__ */ +r3z: lsr.f %r1, %r3, 24 + asl_s %r3, %r3, 8 +#endif /* _ENDIAN__ */ + bne.d r3z + stb.ab %r1, [%r10, 1] + j_s [%blink] + + .balign 4 +charloop: + ldb.ab %r3, [%r1, 1] + brne.d %r3, 0, charloop + stb.ab %r3, [%r10, 1] + j [%blink] diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S new file mode 100644 index 0000000..666e22c --- /dev/null +++ b/arch/arc/lib/strlen.S @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global strlen +.align 4 +strlen: + or %r3, %r0, 7 + ld %r2, [%r3, -7] + ld.a %r6, [%r3, -3] + mov %r4, 0x01010101 + /* uses long immediate */ +#ifdef __LITTLE_ENDIAN__ + asl_s %r1, %r0, 3 + btst_s %r0, 2 + asl %r7, %r4, %r1 + ror %r5, %r4 + sub %r1, %r2, %r7 + bic_s %r1, %r1, %r2 + mov.eq %r7, %r4 + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#else /* __BIG_ENDIAN__ */ + ror %r5, %r4 + btst_s %r0, 2 + mov_s %r1, 31 + sub3 %r7, %r1, %r0 + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + bmsk %r1, %r1, %r7 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + bmsk.ne %r12, %r12, %r7 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#endif /* _ENDIAN__ */ + +.Loop: + ld_s %r2, [%r3, 4] + ld.a %r6, [%r3, 8] + /* stall for load result */ + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + or %r12, %r12, %r1 + and %r12, %r12, %r5 + breq %r12, 0, .Loop +.Lend: + and.f %r1, %r1, %r5 + sub.ne %r3, %r3, 4 + mov.eq %r1, %r12 +#ifdef __LITTLE_ENDIAN__ + sub_s %r2, %r1, 1 + bic_s %r2, %r2, %r1 + norm %r1, %r2 + sub_s %r0, %r0, 3 + lsr_s %r1, %r1, 3 + sub %r0, %r3, %r0 + j_s.d [%blink] + sub %r0, %r0, %r1 +#else /* __BIG_ENDIAN__ */ + lsr_s %r1, %r1, 7 + mov.eq %r2, %r6 + bic_s %r1, %r1, %r2 + norm %r1, %r1 + sub %r0, %r3, %r0 + lsr_s %r1, %r1, 3 + j_s.d [%blink] + add %r0, %r0, %r1 +#endif /* _ENDIAN */ +.Learly_end: + b.d .Lend + sub_s.ne %r1, %r1, %r1 diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 69fff32..52e0f4a 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -66,7 +66,18 @@ u32 spl_boot_device(void) u32 spl_boot_mode(void) { - return gd->arch.omap_boot_params.omap_bootmode; + u32 val = gd->arch.omap_boot_params.omap_bootmode; + + if (val == MMCSD_MODE_RAW) + return MMCSD_MODE_RAW; + else if (val == MMCSD_MODE_FAT) + return MMCSD_MODE_FAT; + else +#ifdef CONFIG_SUPPORT_EMMC_BOOT + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_UNDEFINED; +#endif } void spl_board_init(void) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739d..a7ca12c 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h index 1fec7f3..ab7fa45 100644 --- a/arch/blackfin/cpu/initcode.h +++ b/arch/blackfin/cpu/initcode.h @@ -49,7 +49,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('a'); -#ifdef __ADSPBF60x__ +#ifndef __ADSPBF60x__ /* Program the async banks controller. */ #ifdef EBIU_AMGCTL bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); @@ -74,7 +74,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('c'); -#else /* __ADSPBF60x__ */ +#else /* __ADSPBF60x__ */ /* Program the static memory controller. */ # ifdef CONFIG_SMC_GCTL_VAL bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL); @@ -116,7 +116,7 @@ program_async_controller(ADI_BOOT_DATA *bs) bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL); # endif -#endif +#endif /* __ADSPBF60x__ */ serial_putc('d'); } diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index c99cf49..29a7c23 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -190,6 +190,7 @@ ENTRY(_start) call _memcpy_ASM; #endif +.Lnorelocate: /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR * takes care of clearing things for us. @@ -202,7 +203,6 @@ ENTRY(_start) r2.h = __bss_len; call _memset; -.Lnorelocate: /* Setup the actual stack in external memory */ sp.h = HI(CONFIG_STACKBASE); diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h index 7a43bbb..4c9bc9d 100644 --- a/arch/blackfin/include/asm/mach-common/bits/emac.h +++ b/arch/blackfin/include/asm/mach-common/bits/emac.h @@ -217,4 +217,7 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/*default value for EMAC_VLANx reg*/ +#define EMAC_VLANX_DEF_VAL 0xFFFF + #endif diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 392d72d..facbc7a 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -142,7 +142,8 @@ void init_cplbtables(void) ++i; #if defined(__ADSPBF60x__) icplb_add(0x0, 0x0); - dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID); ++i; #endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 6e201f2..4955e81 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -8,3 +8,4 @@ extra-y = start.o obj-y = irq.o obj-y += cpu.o interrupts.o cache.o exception.o timer.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index 9218355..227842f 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -35,6 +35,9 @@ void _hw_exception_handler (void) puts ("Divide by zero exception\n"); break; #ifdef MICROBLAZE_V5 + case 0x7: + puts("Priviledged or stack protection violation exception\n"); + break; case 0x1000: puts ("Exception in delay slot\n"); break; diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c new file mode 100644 index 0000000..0912261 --- /dev/null +++ b/arch/microblaze/cpu/spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +bool boot_linux; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +/* Board initialization after bss clearance */ +void spl_board_init(void) +{ + gd = (gd_t *)CONFIG_SPL_STACK_ADDR; + + /* enable console uart printing */ + preloader_console_init(); +} + +#ifdef CONFIG_SPL_OS_BOOT +void __noreturn jump_to_image_linux(void *arg) +{ + debug("Entering kernel arg pointer: 0x%p\n", arg); + typedef void (*image_entry_arg_t)(char *, ulong, ulong) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t)spl_image.entry_point; + + image_entry(NULL, 0, (ulong)arg); +} +#endif /* CONFIG_SPL_OS_BOOT */ + +int spl_start_uboot(void) +{ +#ifdef CONFIG_SPL_OS_BOOT + if (boot_linux) + return 0; +#endif + + return 1; +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8928024..1757bbf 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -22,6 +22,11 @@ _start: */ mts rmsr, r0 /* disable cache */ + +#if defined(CONFIG_SPL_BUILD) + addi r1, r0, CONFIG_SPL_STACK_ADDR + addi r1, r1, -4 /* Decrement SP to top of memory */ +#else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -115,6 +120,7 @@ _start: sh r7, r0, r8 rsubi r8, r10, 0x26 sh r6, r0, r8 +#endif /* BUILD_SPL */ /* Flush cache before enable cache */ addik r5, r0, 0 @@ -139,9 +145,14 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifndef CONFIG_SPL_BUILD brai board_init_f +#else + brai board_init_r +#endif 1: bri 1b +#ifndef CONFIG_SPL_BUILD /* * Read 16bit little endian */ @@ -174,3 +185,4 @@ out16: bslli r3, r6, 8 rtsd r15, 8 or r0, r0, r0 .end out16 +#endif diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 69ae6d4..3960bbb 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -34,6 +34,7 @@ void __udelay(unsigned long usec) } } +#ifndef CONFIG_SPL_BUILD static void timer_isr(void *arg) { timestamp++; @@ -62,10 +63,15 @@ int timer_init (void) if (ret) tmr = NULL; } - /* No problem if timer is not found/initialized */ return 0; } +#else +int timer_init(void) +{ + return 0; +} +#endif /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds new file mode 100644 index 0000000..96353cd --- /dev/null +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + arch/microblaze/cpu/start.o (.text) + *(.text) + *(.text.*) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + *(.data.*) + __data_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.sbss) + *(.scommon) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } + __end = . ; +} + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h new file mode 100644 index 0000000..c1cae6c --- /dev/null +++ b/arch/microblaze/include/asm/spl.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MICROBLAZE_SPL_H_ +#define _ASM_MICROBLAZE_SPL_H_ + +#define BOOT_DEVICE_RAM 1 +#define BOOT_DEVICE_NOR 2 +#define BOOT_DEVICE_SPI 3 + +#endif diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index 31b014c..ab3f232 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -25,6 +25,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ unsigned int bi_baudrate; /* Console Baudrate */ + ulong bi_boot_params; /* where this board expects params */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 896e73a..59956a8 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -24,6 +24,12 @@ DECLARE_GLOBAL_DATA_PTR; +static int display_banner(void) +{ + printf("\n\n%s\n\n", version_string); + return 0; +} + /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -44,9 +50,14 @@ init_fnc_t *init_sequence[] = { fdtdec_check_fdt, #endif serial_init, +#ifndef CONFIG_SPL_BUILD console_init_f, +#endif + display_banner, +#ifndef CONFIG_SPL_BUILD interrupts_init, timer_init, +#endif NULL, }; @@ -59,7 +70,7 @@ void board_init_f(ulong not_used) gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET); bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - GENERATED_BD_INFO_SIZE); -#if defined(CONFIG_CMD_FLASH) +#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD) ulong flash_size = 0; #endif asm ("nop"); /* FIXME gd is not initialize - wait */ @@ -81,9 +92,12 @@ void board_init_f(ulong not_used) /* FDT is at end of image */ gd->fdt_blob = (void *)__end; #endif + +#ifndef CONFIG_SPL_BUILD /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, (uintptr_t)gd->fdt_blob); +#endif /* * The Malloc area is immediately below the monitor copy in DRAM @@ -103,6 +117,7 @@ void board_init_f(ulong not_used) hang(); } +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_OF_CONTROL /* For now, put this check after the console is ready */ if (fdtdec_prepare_fdt()) @@ -183,4 +198,5 @@ void board_init_f(ulong not_used) WATCHDOG_RESET(); main_loop(); } +#endif /* CONFIG_SPL_BUILD */ } diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c index 92ada8a..cfe52d1 100644 --- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c +++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c @@ -21,6 +21,7 @@ int main(void) #endif BLANK(); #ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); OFFSET(FTAHBC020S_CR, ftahbc02s, cr); #endif diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 810326d..d6484b9 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -32,6 +32,15 @@ #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR + +/* + * for Orca and Emerald + */ +#define BOARD_ID_REG 0x104 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 + /* * parameters for the static memory controller */ @@ -47,6 +56,10 @@ #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) +/* + * for Orca and Emerald + */ +#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 /* @@ -100,14 +113,49 @@ mem_init: * we need to set onboard SDRAM before remap and relocation. */ led 0x01 - write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052 - write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151 + + /* + * for Orca and Emerald + * disable write protection and reset bank size + */ + li $r0, SMC_BANK0_CR_A + lwi $r1, [$r0+#0x00] + ori $r1, $r1, 0x8f0 + xori $r1, $r1, 0x8f0 + /* + * check board + */ + li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG + lwi $r3, [$r3] + li $r4, BOARD_ID_FAMILY_MASK + and $r3, $r3, $r4 + li $r4, BOARD_ID_FAMILY_K7 + xor $r4, $r3, $r4 + beqz $r4, use_flash_16bit_boot + /* + * 32-bit mode + */ +use_flash_32bit_boot: + ori $r1, $r1, 0x50 + li $r2, 0x00151151 + j sdram_b0_cr + /* + * 16-bit mode + */ +use_flash_16bit_boot: + ori $r1, $r1, 0x60 + li $r2, 0x00153153 + /* + * SRAM bank0 config + */ +sdram_b0_cr: + swi $r1, [$r0+#0x00] + swi $r2, [$r0+#0x04] /* * config AHB Controller */ led 0x02 - write32 AHBC_BSR6_A, AHBC_BSR6_D /* * config PMU controller @@ -194,7 +242,16 @@ relo_base: * a FLASH connected to bank0. */ led 0x11 - li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ + /* + * for Orca and Emerald + * read sdram base address automatically + */ + li $r5, AHBC_BSR6_A + lwi $r8, [$r5] + li $r4, 0xfff00000 + and $r4, $r4, $r8 + + li $r5, 0x0 la $r1, relo_base /* get $pc or $lp */ sub $r2, $r0, $r1 @@ -218,6 +275,29 @@ relo_base: write32 SDMC_B1_BSR_A, 0x00001040 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 + /* + * for Orca and Emerald + * extend sdram size from 256MB to 2GB + */ + li $r5, AHBC_BSR6_A + lwi $r6, [$r5] + li $r4, 0xfff0ffff + and $r6 ,$r4 , $r6 + li $r4, 0x000b0000 + or $r6, $r4, $r6 + swi $r6, [$r5] + + /* + * for Orca and Emerald + * extend rom base from 256MB to 2GB + */ + li $r4, AHBC_BSR4_A + lwi $r5, [$r4] + li $r6, 0xffffff + and $r5, $r5, $r6 + li $r6, 0x80000000 + or $r5, $r5, $r6 + swi $r5, [$r4] #endif /* #ifdef CONFIG_MEM_REMAP */ move $lp, $r11 2: diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 25db899..70e09ea 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -75,6 +75,8 @@ static const char *serdes_prtcl_str[] = { [XFI_FM2_MAC9] = "XFI_FM2_MAC9", [XFI_FM2_MAC10] = "XFI_FM2_MAC10", [INTERLAKEN] = "INTERLAKEN", + [QSGMII_SW1_A] = "QSGMII_SW1_A", + [QSGMII_SW1_B] = "QSGMII_SW1_B", }; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 32075ce..68160a9 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -21,21 +21,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(8, 34, 1, 3), SET_QP_INFO(9, 35, 1, 0), SET_QP_INFO(10, 36, 1, 0), - SET_QP_INFO(11, 37, 1, 1), - SET_QP_INFO(12, 38, 1, 1), - SET_QP_INFO(13, 39, 1, 2), - SET_QP_INFO(14, 40, 1, 2), - SET_QP_INFO(15, 41, 1, 3), - SET_QP_INFO(16, 42, 1, 3), - SET_QP_INFO(17, 43, 1, 0), - SET_QP_INFO(18, 44, 1, 0), - SET_QP_INFO(19, 45, 1, 1), - SET_QP_INFO(20, 46, 1, 1), - SET_QP_INFO(21, 47, 1, 2), - SET_QP_INFO(22, 48, 1, 2), - SET_QP_INFO(23, 49, 1, 3), - SET_QP_INFO(24, 50, 1, 3), - SET_QP_INFO(25, 51, 1, 0), }; #endif @@ -60,11 +45,6 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), - /* SET_NEXUS_LIODN(557), -- not yet implemented */ }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); @@ -77,8 +57,6 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), - SET_FMAN_RX_10G_LIODN(1, 0, 94), - SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif @@ -97,23 +75,9 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); -#ifdef CONFIG_SYS_DPAA_RMAN -struct liodn_id_table rman_liodn_tbl[] = { - /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 678), - SET_RMAN_LIODN(1, 679), - SET_RMAN_LIODN(2, 680), - SET_RMAN_LIODN(3, 681), -}; -int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); -#endif - struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), #endif -#ifdef CONFIG_SYS_DPAA_RMAN - [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), -#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 94814ac..d86bb27 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -8,68 +8,59 @@ #include #include #include -#include "fsl_corenet2_serdes.h" -static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = { - { /* SerDes 1 */ - [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, SATA2, SATA1}, + [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE2, PCIE2, PCIE2}, [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, PCIE2, PCIE3, PCIE4, SATA1}, [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE2, PCIE2, PCIE2}, - [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5}, - [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1}, + [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE3, PCIE4, SATA1}, + [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE2, PCIE2, PCIE2}, - [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE3, PCIE4, SATA1}, - [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE3, SATA2, SATA1}, + [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, PCIE3, QSGMII_SW1_B, SATA1}, + [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B}, [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE2, PCIE2, PCIE2}, - }, - { - }, - { - }, - { - }, + [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, }; - enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) { - return serdes_cfg_tbl[serdes][cfg][lane]; + return serdes_cfg_tbl[cfg][lane]; } int is_serdes_prtcl_valid(int serdes, u32 prtcl) { int i; - if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes])) + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[serdes][prtcl][i] != NONE) + if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index be1d9d2..56587ae 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -22,6 +22,9 @@ #define FSL_DDR_VER_4_7 47 #define FSL_DDR_VER_5_0 50 +/* IP endianness */ +#define CONFIG_SYS_FSL_IFC_BE + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -717,8 +720,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 404ded4..f60cb0a 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -69,13 +69,7 @@ enum srds_prtcl { XFI_FM2_MAC9, XFI_FM2_MAC10, INTERLAKEN, - SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ - SGMII_SW1_DTSEC2, - SGMII_SW1_DTSEC3, - SGMII_SW1_DTSEC4, - SGMII_SW1_DTSEC5, - SGMII_SW1_DTSEC6, - QSGMII_SW1_A, /* SW indicates on L2 swtich */ + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ QSGMII_SW1_B, }; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c82..9d08321 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,6 +1759,17 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 58c2537..b564294 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,7 +10,7 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) -$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) +$(obj)os.o: CFLAGS := $(filter-out -nostdinc,\ + $(patsubst -I%,-idirafter%,$(CFLAGS))) +$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,\ + $(patsubst -I%,-idirafter%,$(CPPFLAGS))) diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index aa126d7..5ab9471 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -16,7 +16,8 @@ void text_base_hook(void); /* nop hook for text_base.S */ -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) static void __early_flash_cmd_reset(void) { /* reset flash before we read env */ @@ -37,7 +38,8 @@ int board_early_init_f(void) "led"); #endif #endif -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) early_flash_cmd_reset(); #endif return 0; diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index cfc64fe..43a4330 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + ret += designware_initialize(EMAC0_MACCFG, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + ret += designware_initialize(EMAC1_MACCFG, 0); } return ret; diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 3f4cfa1..d9c05b0 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -389,7 +389,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_MV_UDC +#ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); #endif diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 93af9eb..c7470d7 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -9,3 +9,4 @@ obj-y += ddr.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += eth.o diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index 6d380ae..8160ca0 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -121,14 +121,14 @@ NOR Flash memory Map on T1040QDS 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB -0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c new file mode 100644 index 0000000..3077b4a --- /dev/null +++ b/board/freescale/t1040qds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY connected to + * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board + * PHY or by the standard four-port SGMII riser card (VSC). + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "../common/qixis.h" + +#include "t1040qds_qixis.h" + +#ifdef CONFIG_FMAN_ENET + /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D + * Bank 2 -> Lanes E, F, G, H + */ + + /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII0 0 +#define EMI1_RGMII1 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1040_QDS_MDIO0", + "T1040_QDS_MDIO1", + "T1040_QDS_MDIO2", + "T1040_QDS_MDIO3", + "T1040_QDS_MDIO4", + "T1040_QDS_MDIO5", + "T1040_QDS_MDIO6", + "T1040_QDS_MDIO7", +}; + +struct t1040_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t1040_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void t1040_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval <= 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1040_qds_mdio_reset(struct mii_dev *bus) +{ + struct t1040_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1040_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1040_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1040_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1040_qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1040_qds_mdio_read; + bus->write = t1040_qds_mdio_write; + bus->reset = t1040_qds_mdio_reset; + sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the lane_to_slot[] array. + * + * On the T1040QDS board the mapping is controlled by ?? register. + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL) + >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + QIXIS_WRITE(cms[0], 0x07); + + switch (serdes1_prtcl) { + case 0x60: + case 0x66: + case 0x67: + case 0x69: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + break; + case 0x86: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + case 0x87: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x89: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x8d: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0x8F: + case 0x85: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA5: + lane_to_slot[1] = 7; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA7: + lane_to_slot[1] = 7; + lane_to_slot[7] = 7; + break; + case 0xAA: + lane_to_slot[1] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x40: + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + default: + printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + /* Slot housing a SGMII riser card */ + sprintf(phy, "phy_s%x_%02x", slot, + (fm_info_get_phy_address(port - FM1_DTSEC1)- + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT5: + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + break; + case EMI1_SLOT6: + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + break; + case EMI1_SLOT7: + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC4) + fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); + + if (i == FM1_DTSEC5) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + break; + default: + break; + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +static void set_brdcfg9_for_gtx_clk(void) +{ + u8 brdcfg9; + brdcfg9 = QIXIS_READ(brdcfg[9]); + brdcfg9 |= (1 << 5); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +void t1040_handle_phy_interface_sgmii(int i) +{ + int lane, idx, slot; + idx = i - FM1_DTSEC1; + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + + if (lane < 0) + return; + slot = lane_to_slot[lane]; + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + if (FM1_DTSEC4 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + + mdio_mux[i] = EMI1_SLOT3; + + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 5: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 6: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 7: + if (FM1_DTSEC1 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC2 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + if (FM1_DTSEC3 == i) + fm_info_set_phy_address(i, riser_phy_addr[2]); + + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} +void t1040_handle_phy_interface_rgmii(int i) +{ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : + EMI1_RGMII0; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + set_brdcfg9_for_gtx_clk(); + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + + /* + * Program on board RGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + break; + case PHY_INTERFACE_MODE_SGMII: + t1040_handle_phy_interface_sgmii(i); + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + t1040_handle_phy_interface_rgmii(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index de3ea5c..3dec447 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); #endif } diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 76c0c94..e51fb7a 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -7,6 +7,7 @@ obj-y += t104xrdb.o obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 11e03bd..1da52bb 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -164,14 +164,14 @@ NOR Flash memory Map 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB -0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c new file mode 100644 index 0000000..0188fd4 --- /dev/null +++ b/board/freescale/t104xrdb/eth.c @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + int phy_addr = 0; + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { +#ifdef CONFIG_T1040RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1040RDB only supports SGMII on DTSEC3 */ + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_SGMII1_PHY_ADDR); +#endif + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile index 3e69ee2..c57ca08 100644 --- a/board/keymile/kmp204x/Makefile +++ b/board/keymile/kmp204x/Makefile @@ -8,5 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \ +obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \ ../common/common.o ../common/ivm.o diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index f02642a..95a19cd 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -33,12 +33,51 @@ int checkboard(void) return 0; } -/* TODO: implement the I2C deblocking function */ -int i2c_make_abort(void) +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines + * For I2C only the low state is activly driven and high state is pulled-up + * by a resistor. Therefore the deblock GPIOs are used + * -> as an active output to drive a low state + * -> as an open-drain input to have a pulled-up high state + */ + +/* QRIO GPIOs used for deblocking */ +#define DEBLOCK_PORT1 GPIO_A +#define DEBLOCK_SCL1 20 +#define DEBLOCK_SDA1 21 + +/* By default deblock GPIOs are floating */ +static void i2c_deblock_gpio_cfg(void) +{ + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); + + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); +} + +void set_sda(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); +} + +int get_scl(void) { - return 1; + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); } + #define ZL30158_RST 8 #define ZL30343_RST 9 @@ -62,6 +101,7 @@ int board_early_init_f(void) int board_early_init_r(void) { + int ret = 0; /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); @@ -69,7 +109,11 @@ int board_early_init_r(void) set_liodns(); setup_portals(); - return 0; + ret = trigger_fpga_config(); + if (ret) + printf("error triggering PCIe FPGA config\n"); + + return ret; } unsigned long get_board_sys_clk(unsigned long dummy) @@ -77,80 +121,12 @@ unsigned long get_board_sys_clk(unsigned long dummy) return 66666666; } -#define WDMASK_OFF 0x16 - -static void qrio_wdmask(u8 bit, bool wden) -{ - u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - wdmask = in_be16(qrio_base + WDMASK_OFF); - - if (wden) - wdmask |= (1 << bit); - else - wdmask &= ~(1 << bit); - - out_be16(qrio_base + WDMASK_OFF, wdmask); -} - -#define PRST_OFF 0x1a - -void qrio_prst(u8 bit, bool en, bool wden) -{ - u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - qrio_wdmask(bit, wden); - - prst = in_be16(qrio_base + PRST_OFF); - - if (en) - prst &= ~(1 << bit); - else - prst |= (1 << bit); - - out_be16(qrio_base + PRST_OFF, prst); -} - -#define PRSTCFG_OFF 0x1c - -void qrio_prstcfg(u8 bit, u8 mode) -{ - u32 prstcfg; - u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - prstcfg = in_be32(qrio_base + PRSTCFG_OFF); - - for (i = 0; i < 2; i++) { - if (mode & (1< #include #include +#include #include "kmp204x.h" +#define PROM_SEL_L 11 +/* control the PROM_SEL_L signal*/ +static void toggle_fpga_eeprom_bus(bool cpu_own) +{ + qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); +} + +#define CONF_SEL_L 10 +#define FPGA_PROG_L 19 +#define FPGA_DONE 18 +#define FPGA_INIT_L 17 + +int trigger_fpga_config(void) +{ + int ret = 0, init_l; + /* approx 10ms */ + u32 timeout = 10000; + + /* make sure the FPGA_can access the EEPROM */ + toggle_fpga_eeprom_bus(false); + + /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ + qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); + + /* trigger the config start */ + qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); + + /* small delay for INIT_L line */ + udelay(10); + + /* wait for FPGA_INIT to be asserted */ + do { + init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); + if (timeout-- == 0) { + printf("FPGA_INIT timeout\n"); + ret = -EFAULT; + break; + } + udelay(10); + } while (init_l); + + /* deassert FPGA_PROG, config should start */ + qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); + + return ret; +} + +/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ +static int wait_for_fpga_config(void) +{ + int ret = 0, done; + /* approx 5 s */ + u32 timeout = 500000; + + printf("PCIe FPGA config:"); + do { + done = qrio_get_gpio(GPIO_A, FPGA_DONE); + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + ret = -EFAULT; + goto err_out; + } + udelay(10); + } while (!done); + + printf(" done\n"); + +err_out: + /* deactive CONF_SEL and give the CPU conf EEPROM access */ + qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); + toggle_fpga_eeprom_bus(true); + + return ret; +} + #define PCIE_SW_RST 14 +#define PEXHC_SW_RST 13 #define HOOPER_SW_RST 12 void pci_init_board(void) { + /* first wait for the PCIe FPGA to be configured + * it has been triggered earlier in board_early_init_r */ + int ret = wait_for_fpga_config(); + if (ret) + printf("error finishing PCIe FPGA config\n"); + qrio_prst(PCIE_SW_RST, false, false); + qrio_prst(PEXHC_SW_RST, false, false); qrio_prst(HOOPER_SW_RST, false, false); /* Hooper is not direcly PCIe capable */ mdelay(50); + fsl_pcie_init_board(0); } diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c new file mode 100644 index 0000000..49f9aa2 --- /dev/null +++ b/board/keymile/kmp204x/qrio.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../common/common.h" +#include "kmp204x.h" + +/* QRIO GPIO register offsets */ +#define DIRECT_OFF 0x18 +#define GPRT_OFF 0x1c + +int qrio_get_gpio(u8 port_off, u8 gpio_nr) +{ + u32 gprt; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + + return (gprt >> gpio_nr) & 1U; +} + +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) +{ + u32 gprt, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + if (value) + gprt |= mask; + else + gprt &= ~mask; + + out_be32(qrio_base + port_off + GPRT_OFF, gprt); +} + +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct |= mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); + + qrio_set_gpio(port_off, gpio_nr, value); +} + +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct &= ~mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + if (val == 0) + /* set to output -> GPIO drives low */ + direct |= mask; + else + /* set to input -> GPIO floating */ + direct &= ~mask; + + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +#define WDMASK_OFF 0x16 + +static void qrio_wdmask(u8 bit, bool wden) +{ + u16 wdmask; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + wdmask = in_be16(qrio_base + WDMASK_OFF); + + if (wden) + wdmask |= (1 << bit); + else + wdmask &= ~(1 << bit); + + out_be16(qrio_base + WDMASK_OFF, wdmask); +} + +#define PRST_OFF 0x1a + +void qrio_prst(u8 bit, bool en, bool wden) +{ + u16 prst; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + qrio_wdmask(bit, wden); + + prst = in_be16(qrio_base + PRST_OFF); + + if (en) + prst &= ~(1 << bit); + else + prst |= (1 << bit); + + out_be16(qrio_base + PRST_OFF, prst); +} + +#define PRSTCFG_OFF 0x1c + +void qrio_prstcfg(u8 bit, u8 mode) +{ + u32 prstcfg; + u8 i; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + prstcfg = in_be32(qrio_base + PRSTCFG_OFF); + + for (i = 0; i < 2; i++) { + if (mode & (1<= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 70f9aa1..a4c6a8e 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index f6b1fdd..ab732a7 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index e996a0e..8472002 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 044d204..b8edfcd 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,31 +67,32 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); + phy_reset(phydev); /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++; diff --git a/board/synopsys/arcangel4/Makefile b/board/synopsys/arcangel4/Makefile new file mode 100644 index 0000000..575e58f --- /dev/null +++ b/board/synopsys/arcangel4/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# This board is mostly used for debugging U-Boot in simulation (ISS). +# The only peripheral which is used on this board is a serial port which +# requires no initialization except those in "include/configs/arcangel4.h". +# And now there's no specific initializations for this board. +# So this Makefile is only required for satisfaction of U-Boot build system. diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile new file mode 100644 index 0000000..f0965f7 --- /dev/null +++ b/board/synopsys/axs101/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += axs101.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c new file mode 100644 index 0000000..4dbeaea --- /dev/null +++ b/board/synopsys/axs101/axs101.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 25000000; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(0, ARC_DWGMAC_BASE, 0, + PHY_INTERFACE_MODE_RGMII) >= 0) + return 1; + + return 0; +} diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c new file mode 100644 index 0000000..8672803 --- /dev/null +++ b/board/synopsys/axs101/nand.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define BUS_WIDTH 8 /* AXI data bus width in bytes */ + +/* DMA buffer descriptor bits & masks */ +#define BD_STAT_OWN (1 << 31) +#define BD_STAT_BD_FIRST (1 << 3) +#define BD_STAT_BD_LAST (1 << 2) +#define BD_SIZES_BUFFER1_MASK 0xfff + +#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) + +/* Controller command flags */ +#define B_WFR (1 << 19) /* 1b - Wait for ready */ +#define B_LC (1 << 18) /* 1b - Last cycle */ +#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ + +/* NAND cycle types */ +#define B_CT_ADDRESS (0x0 << 16) /* Address operation */ +#define B_CT_COMMAND (0x1 << 16) /* Command operation */ +#define B_CT_WRITE (0x2 << 16) /* Write operation */ +#define B_CT_READ (0x3 << 16) /* Write operation */ + +enum nand_isr_t { + NAND_ISR_DATAREQUIRED = 0, + NAND_ISR_TXUNDERFLOW, + NAND_ISR_TXOVERFLOW, + NAND_ISR_DATAAVAILABLE, + NAND_ISR_RXUNDERFLOW, + NAND_ISR_RXOVERFLOW, + NAND_ISR_TXDMACOMPLETE, + NAND_ISR_RXDMACOMPLETE, + NAND_ISR_DESCRIPTORUNAVAILABLE, + NAND_ISR_CMDDONE, + NAND_ISR_CMDAVAILABLE, + NAND_ISR_CMDERROR, + NAND_ISR_DATATRANSFEROVER, + NAND_ISR_NONE +}; + +enum nand_regs_t { + AC_FIFO = 0, /* address and command fifo */ + IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */ + INT_STATUS = 0x118, /* interrupt status register */ + INT_CLR_STATUS = 0x120, /* interrupt clear status register */ +}; + +struct nand_bd { + uint32_t status; /* DES0 */ + uint32_t sizes; /* DES1 */ + uint32_t buffer_ptr0; /* DES2 */ + uint32_t buffer_ptr1; /* DES3 */ +}; + +#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r) +#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r) + +static struct nand_bd *bd; /* DMA buffer descriptors */ + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static uint32_t nand_flag_is_set(uint32_t flag) +{ + uint32_t reg = NAND_REG_READ(INT_STATUS); + + if (reg & (1 << NAND_ISR_CMDERROR)) + return 0; + + if (reg & (1 << flag)) { + NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag); + return 1; + } + + return 0; +} + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Issue "write" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store data + * @len: number of bytes to read + */ +static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Issue "read" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char axs101_nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + + axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * axs101_nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 axs101_nand_read_word(struct mtd_info *mtd) +{ + u16 word; + + axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * axs101_nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, + unsigned int ctrl) +{ + if (cmd == NAND_CMD_NONE) + return; + + cmd = cmd & 0xff; + + switch (ctrl & (NAND_ALE | NAND_CLE)) { + /* Address */ + case NAND_ALE: + cmd |= B_CT_ADDRESS; + break; + + /* Command */ + case NAND_CLE: + cmd |= B_CT_COMMAND | B_WFR; + + break; + + default: + debug("%s: unknown ctrl %#x\n", __func__, ctrl); + } + + NAND_REG_WRITE(AC_FIFO, cmd | B_LC); + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; +} + +int board_nand_init(struct nand_chip *nand) +{ + bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN, + sizeof(struct nand_bd)); + + /* Set buffer descriptor address in IDMAC */ + NAND_REG_WRITE(IDMAC_BDADDR, bd); + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = axs101_nand_hwcontrol; + nand->read_byte = axs101_nand_read_byte; + nand->read_word = axs101_nand_read_word; + nand->write_buf = axs101_nand_write_buf; + nand->read_buf = axs101_nand_read_buf; + + return 0; +} diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README new file mode 100644 index 0000000..2fdaeac --- /dev/null +++ b/board/ti/dra7xx/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'dra7xx_evm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} dra7xx/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} dra7xx/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README new file mode 100644 index 0000000..970e2ec --- /dev/null +++ b/board/ti/omap5_uevm/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'omap5_uevm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} omap5uevm/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index a5b9bde..5a47149 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -23,6 +23,7 @@ Xilinx_desc fpga; /* It can be done differently */ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); @@ -40,6 +41,9 @@ int board_init(void) case XILINX_ZYNQ_7010: fpga = fpga010; break; + case XILINX_ZYNQ_7015: + fpga = fpga015; + break; case XILINX_ZYNQ_7020: fpga = fpga020; break; diff --git a/boards.cfg b/boards.cfg index f6a7488..7a8688a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -992,6 +992,7 @@ Active powerpc mpc85xx - gdsys p1022 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach +Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek @@ -1231,6 +1232,9 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +Active arc arc700 - synopsys - axs101 - Alexey Brodkin +Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski Orphan arm pxa - - - lubbock - (dead address) Kyle Harris diff --git a/common/Makefile b/common/Makefile index 4d99ecd..a83246e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 713de14..15119a7 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -517,6 +517,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_ARC700) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("mem start", bd->bi_memstart); + print_lnum("mem size", bd->bi_memsize); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf("ip_addr = %s\n", getenv("ipaddr")); +#endif + printf("baudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index da5fef9..2d51927 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -131,36 +131,6 @@ U_BOOT_CMD( "- display info of the current MMC device" ); -#ifdef CONFIG_SUPPORT_EMMC_BOOT -static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - err = mmc_boot_part_access(mmc, ack, part_num, access); - - if ((err == 0) && (access != 0)) { - printf("\t\t\t!!!Notice!!!\n"); - - printf("!You must close EMMC boot Partition"); - printf("after all images are written\n"); - - printf("!EMMC boot partition has continuity"); - printf("at image writing time.\n"); - - printf("!So, do not close the boot partition"); - printf("before all images are written.\n"); - return 0; - } else if ((err == 0) && (access == 0)) - return 0; - else if ((err != 0) && (access != 0)) { - printf("EMMC boot partition-%d OPEN Failed.\n", part_num); - return 1; - } else { - printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); - return 1; - } -} -#endif - static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -195,7 +165,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; else return 0; - } else if (strncmp(argv[1], "part", 4) == 0) { + } else if (strcmp(argv[1], "part") == 0) { block_dev_desc_t *mmc_dev; struct mmc *mmc; @@ -273,15 +243,16 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if ((strcmp(argv[1], "open") == 0) || - (strcmp(argv[1], "close") == 0)) { + } else if (strcmp(argv[1], "partconf") == 0) { int dev; struct mmc *mmc; - u8 part_num, access = 0; + u8 ack, part_num, access; - if (argc == 4) { + if (argc == 6) { dev = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); + ack = simple_strtoul(argv[3], NULL, 10); + part_num = simple_strtoul(argv[4], NULL, 10); + access = simple_strtoul(argv[5], NULL, 10); } else { return CMD_RET_USAGE; } @@ -293,32 +264,53 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (IS_SD(mmc)) { - printf("SD device cannot be opened/closed\n"); + puts("PARTITION_CONFIG only exists on eMMC\n"); return 1; } - if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { - printf("Invalid boot partition number:\n"); - printf("Boot partition number cannot be <= 0\n"); - printf("EMMC44 supports only 2 boot partitions\n"); + /* acknowledge to be sent during boot operation */ + return mmc_set_part_conf(mmc, ack, part_num, access); + } else if (strcmp(argv[1], "bootbus") == 0) { + int dev; + struct mmc *mmc; + u8 width, reset, mode; + + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + width = simple_strtoul(argv[3], NULL, 10); + reset = simple_strtoul(argv[4], NULL, 10); + mode = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); return 1; } - if (strcmp(argv[1], "open") == 0) - access = part_num; /* enable R/W access to boot part*/ - else - access = 0; /* No access to boot partition */ + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return 1; + } /* acknowledge to be sent during boot operation */ - return boot_part_access(mmc, 1, part_num, access); - - } else if (strcmp(argv[1], "bootpart") == 0) { + return mmc_set_boot_bus_width(mmc, width, reset, mode); + } else if (strcmp(argv[1], "bootpart-resize") == 0) { int dev; - dev = simple_strtoul(argv[2], NULL, 10); + struct mmc *mmc; + u32 bootsize, rpmbsize; - u32 bootsize = simple_strtoul(argv[3], NULL, 10); - u32 rpmbsize = simple_strtoul(argv[4], NULL, 10); - struct mmc *mmc = find_mmc_device(dev); + if (argc == 5) { + dev = simple_strtoul(argv[2], NULL, 10); + bootsize = simple_strtoul(argv[3], NULL, 10); + rpmbsize = simple_strtoul(argv[4], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); if (!mmc) { printf("no mmc device at slot %x\n", dev); return 1; @@ -438,12 +430,12 @@ U_BOOT_CMD( "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc open \n" - " - Enable boot_part for booting and enable R/W access of boot_part\n" - "mmc close \n" - " - Enable boot_part for booting and disable access to boot_part\n" - "mmc bootpart \n" - " - change sizes of boot and RPMB partitions of specified device\n" + "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + " - Set the BOOT_BUS_WIDTH field of the specified device\n" + "mmc bootpart-resize \n" + " - Change sizes of boot and RPMB partitions of specified device\n" + "mmc partconf dev boot_ack boot_partition partition_access\n" + " - Change the bits of the PARTITION_CONFIG field of the specified device\n" #endif "mmc setdsr - set DSR register value\n" ); diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index c27ec35..29e48db 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "menu.h" @@ -160,6 +161,19 @@ static int do_get_fat(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) return -ENOENT; } +static int do_get_any(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) +{ +#ifdef CONFIG_CMD_FS_GENERIC + fs_argv[0] = "load"; + fs_argv[3] = file_addr; + fs_argv[4] = (void *)file_path; + + if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY)) + return 1; +#endif + return -ENOENT; +} + /* * As in pxelinux, paths to files referenced from files we retrieve are * relative to the location of bootfile. get_relfile takes such a path and @@ -445,6 +459,7 @@ struct pxe_label { char *append; char *initrd; char *fdt; + char *fdtdir; int ipappend; int attempted; int localboot; @@ -517,6 +532,9 @@ static void label_destroy(struct pxe_label *label) if (label->fdt) free(label->fdt); + if (label->fdtdir) + free(label->fdtdir); + free(label); } @@ -675,13 +693,67 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) bootm_argv[3] = getenv("fdt_addr_r"); /* if fdt label is defined then get fdt from server */ - if (bootm_argv[3] && label->fdt) { - if (get_relfile_envaddr(cmdtp, label->fdt, "fdt_addr_r") < 0) { - printf("Skipping %s for failure retrieving fdt\n", - label->name); - return 1; + if (bootm_argv[3]) { + char *fdtfile = NULL; + char *fdtfilefree = NULL; + + if (label->fdt) { + fdtfile = label->fdt; + } else if (label->fdtdir) { + fdtfile = getenv("fdtfile"); + /* + * For complex cases, it might be worth calling a + * board- or SoC-provided function here to provide a + * better default: + * + * if (!fdtfile) + * fdtfile = gen_fdtfile(); + * + * If this is added, be sure to keep the default below, + * or move it to the default weak implementation of + * gen_fdtfile(). + */ + if (!fdtfile) { + char *soc = getenv("soc"); + char *board = getenv("board"); + char *slash; + + len = strlen(label->fdtdir); + if (!len) + slash = "./"; + else if (label->fdtdir[len - 1] != '/') + slash = "/"; + else + slash = ""; + + len = strlen(label->fdtdir) + strlen(slash) + + strlen(soc) + 1 + strlen(board) + 5; + fdtfilefree = malloc(len); + if (!fdtfilefree) { + printf("malloc fail (FDT filename)\n"); + return 1; + } + + snprintf(fdtfilefree, len, "%s%s%s-%s.dtb", + label->fdtdir, slash, soc, board); + fdtfile = fdtfilefree; + } } - } else + + if (fdtfile) { + int err = get_relfile_envaddr(cmdtp, fdtfile, "fdt_addr_r"); + free(fdtfilefree); + if (err < 0) { + printf("Skipping %s for failure retrieving fdt\n", + label->name); + return 1; + } + } else { + bootm_argv[3] = NULL; + } + } + + if (!bootm_argv[3]) bootm_argv[3] = getenv("fdt_addr"); if (bootm_argv[3]) @@ -716,6 +788,7 @@ enum token_type { T_PROMPT, T_INCLUDE, T_FDT, + T_FDTDIR, T_ONTIMEOUT, T_IPAPPEND, T_INVALID @@ -745,7 +818,10 @@ static const struct token keywords[] = { {"append", T_APPEND}, {"initrd", T_INITRD}, {"include", T_INCLUDE}, + {"devicetree", T_FDT}, {"fdt", T_FDT}, + {"devicetreedir", T_FDTDIR}, + {"fdtdir", T_FDTDIR}, {"ontimeout", T_ONTIMEOUT,}, {"ipappend", T_IPAPPEND,}, {NULL, T_INVALID} @@ -1134,6 +1210,11 @@ static int parse_label(char **c, struct pxe_menu *cfg) err = parse_sliteral(c, &label->fdt); break; + case T_FDTDIR: + if (!label->fdtdir) + err = parse_sliteral(c, &label->fdtdir); + break; + case T_LOCALBOOT: label->localboot = 1; err = parse_integer(c, &label->localboot_val); @@ -1539,6 +1620,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) do_getfile = do_get_ext2; else if (strstr(argv[3], "fat")) do_getfile = do_get_fat; + else if (strstr(argv[3], "any")) + do_getfile = do_get_any; else { printf("Invalid filesystem: %s\n", argv[3]); return 1; @@ -1576,7 +1659,7 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sysboot, 7, 1, do_sysboot, "command to get and boot from syslinux files", - "[-p] [addr] [filename]\n" - " - load and parse syslinux menu file 'filename' from ext2 or fat\n" - " filesystem on 'dev' on 'interface' to address 'addr'" + "[-p] [addr] [filename]\n" + " - load and parse syslinux menu file 'filename' from ext2, fat\n" + " or any filesystem on 'dev' on 'interface' to address 'addr'" ); diff --git a/common/image.c b/common/image.c index ae95c3f..9c6bec5 100644 --- a/common/image.c +++ b/common/image.c @@ -82,6 +82,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, { IH_ARCH_ARM64, "arm64", "AArch64", }, + { IH_ARCH_ARC, "arc", "ARC", }, { -1, "", "", }, }; diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 13fbff0..fa6f891 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -111,6 +111,30 @@ void spl_mmc_load_image(void) CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); #endif +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + + if (mmc_switch_part(0, part)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("MMC partition switch failed\n"); +#endif + hang(); + } +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) +#endif + err = mmc_load_image_raw(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); +#endif } else { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("spl: wrong MMC boot mode\n"); diff --git a/config.mk b/config.mk index b824bb3..60e297a 100644 --- a/config.mk +++ b/config.mk @@ -250,16 +250,11 @@ Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) endif endif -# Sandbox needs the base flags and includes, so keep them around -BASE_CPPFLAGS := $(CPPFLAGS) - ifneq ($(OBJTREE),$(SRCTREE)) -BASE_INCLUDE_DIRS := $(OBJTREE)/include +CPPFLAGS += -I$(OBJTREE)/include endif -BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include - -CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS)) +CPPFLAGS += -I$(TOPDIR)/include -I$(SRCTREE)/arch/$(ARCH)/include CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) diff --git a/doc/README.ARC b/doc/README.ARC new file mode 100644 index 0000000..5f414fb --- /dev/null +++ b/doc/README.ARC @@ -0,0 +1,27 @@ +Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs +that SoC designers can optimize for a wide range of uses, from deeply embedded +to high-performance host applications. + +More information on ARC cores avaialble here: +http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx + +Designers can differentiate their products by using patented configuration +technology to tailor each ARC processor instance to meet specific performance, +power and area requirements. + +The DesignWare ARC processors are also extendable, allowing designers to add +their own custom instructions that dramatically increase performance. + +Synopsys' ARC processors have been used by over 170 customers worldwide who +collectively ship more than 1 billion ARC-based chips annually. + +All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent +performance and code density for embedded and host SoC applications. + +The RISC microprocessors are synthesizable and can be implemented in any foundry +or process, and are supported by a complete suite of development tools. + +The ARC GNU toolchain with support for all ARC Processors can be downloaded +from here (available pre-built toolchains as well): + +https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases diff --git a/doc/README.b4860qds b/doc/README.b4860qds index f8a79db..3da77d9 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -230,14 +230,14 @@ NOR Flash memory Map on B4860 and B4420QDS 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB +0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB 0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB 0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB -0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB +0xED300000 0xEDEFFFFF rootfs (current bank) 12MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB 0xEC000000 0xEC01FFFF RCW (current bank) 128KB diff --git a/doc/README.designware_eth b/doc/README.designware_eth deleted file mode 100644 index 25ec6bd..0000000 --- a/doc/README.designware_eth +++ /dev/null @@ -1,25 +0,0 @@ -This driver supports Designware Ethernet Controller provided by Synopsis. - -The driver is enabled by CONFIG_DESIGNWARE_ETH. - -The driver has been developed and tested on SPEAr platforms. By default, the -MDIO interface works at 100/Full. #defining the below options in board -configuration file changes this behavior. - -Call an subroutine from respective board/.../board.c -designware_initialize(u32 id, ulong base_addr, u32 phy_addr); - -The various options suported by the driver are -1. CONFIG_DW_ALTDESCRIPTOR - Define this to use the Alternate/Enhanced Descriptor configurations. -1. CONFIG_DW_AUTONEG - Define this to autonegotiate with the host before proceeding with mac - level configuration. This obviates the definitions of CONFIG_DW_SPEED10M - and CONFIG_DW_DUPLEXHALF. -2. CONFIG_DW_SPEED10M - Define this to change the default behavior from 100Mbps to 10Mbps. -3. CONFIG_DW_DUPLEXHALF - Define this to change the default behavior from Full Duplex to Half. -4. CONFIG_DW_SEARCH_PHY - Define this to search the phy address. This would overwrite the value - passed as 3rd arg from designware_initialize routine. diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 1effbad..15900c9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -187,6 +187,16 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf_start) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aa..d45c15c 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e..de8cdcc 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c6a1c23..8ab0bc9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -430,7 +430,7 @@ int mmc_complete_op_cond(struct mmc *mmc) mmc->ocr = cmd.response[0]; mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); - mmc->rca = 0; + mmc->rca = 1; return 0; } @@ -1442,67 +1442,44 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, } /* - * This function shall form and send the commands to open / close the - * boot partition specified by user. - * - * Input Parameters: - * ack: 0x0 - No boot acknowledge sent (default) - * 0x1 - Boot acknowledge sent during boot operation - * part_num: User selects boot data that will be sent to master - * 0x0 - Device not boot enabled (default) - * 0x1 - Boot partition 1 enabled for boot - * 0x2 - Boot partition 2 enabled for boot - * access: User selects partitions to access - * 0x0 : No access to boot partition (default) - * 0x1 : R/W boot partition 1 - * 0x2 : R/W boot partition 2 - * 0x3 : R/W Replay Protected Memory Block (RPMB) + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. * * Returns 0 on success. */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) { int err; - struct mmc_cmd cmd; - /* Boot ack enable, boot partition enable , boot partition access */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_PART_CONF << 16) | - ((EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)) << 8); + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - if (access) { - debug("mmc boot partition#%d open fail:Error1 = %d\n", - part_num, err); - } else { - debug("mmc boot partition#%d close fail:Error = %d\n", - part_num, err); - } + if (err) return err; - } + return 0; +} - if (access) { - /* 4bit transfer mode at booting time. */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_BOOT_BUS_WIDTH << 16) | - ((1 << 0) << 8); + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc boot partition#%d open fail:Error2 = %d\n", - part_num, err); - return err; - } - } + if (err) + return err; return 0; } #endif diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 610bef5..72a272f 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -23,7 +23,8 @@ int zynq_sdhci_init(u32 regbase) host->name = "zynq_sdhci"; host->ioaddr = (void *)regbase; - host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD; + host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD | + SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->host_caps = MMC_MODE_HC; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1808a7f..be5a16a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -230,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, page_addr); - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + ifc_out32(&ifc->ifc_nand.row0, page_addr); + ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); buf_num = page_addr & priv->bufnum_mask; @@ -294,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read/write seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) printf("%s: Flash Time Out Error\n", __func__); @@ -324,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector + chip->ecc.steps - 1; for (i = sector / 4; i <= sector_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); @@ -364,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip, /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ if (mtd->writesize > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); if (oob) - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); else - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } } @@ -408,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, switch (command) { /* READ0 read the entire buffer to use hardware ECC. */ case NAND_CMD_READ0: { - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); set_addr(mtd, 0, page_addr, 0); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -424,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); set_addr(mtd, column, page_addr, 1); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -441,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_PARAM) timing = IFC_FIR_OP_RBCD; - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (timing << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - command << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, column); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (timing << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + command << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, column); /* * although currently it's 8 bytes for READID, we always read * the maximum 256 bytes(for PARAM) */ - out_be32(&ifc->ifc_nand.nand_fbcr, 256); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 256); ctrl->read_bytes = 256; set_addr(mtd, 0, 0, 0); @@ -468,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* ERASE2 uses the block and page address from ERASE1 */ case NAND_CMD_ERASE2: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); ctrl->read_bytes = 0; fsl_ifc_run_command(mtd); return; @@ -494,17 +494,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << + IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | @@ -513,18 +514,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= @@ -539,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, column -= mtd->writesize; ctrl->oob = 1; } - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); set_addr(mtd, column, page_addr, ctrl->oob); return; } @@ -547,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ case NAND_CMD_PAGEPROG: if (ctrl->oob) - out_be32(&ifc->ifc_nand.nand_fbcr, - ctrl->index - ctrl->column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, + ctrl->index - ctrl->column); else - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); fsl_ifc_run_command(mtd); return; case NAND_CMD_STATUS: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -572,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, return; case NAND_CMD_RESET: - out_be32(&ifc->ifc_nand.nand_fir0, - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); fsl_ifc_run_command(mtd); return; @@ -647,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ctrl->index < ctrl->read_bytes) { - data = in_be16((uint16_t *)&ctrl-> - addr[ctrl->index]); + data = ifc_in16((uint16_t *)&ctrl-> + addr[ctrl->index]); ctrl->index += 2; return (uint8_t)data; } @@ -727,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; /* Use READ_STATUS command, but wait for the device to be ready */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << - IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -741,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); /* Chip sometimes reporting write protect even when it's not */ nand_fsr = nand_fsr | NAND_STATUS_WP; @@ -784,17 +785,17 @@ static void fsl_ifc_ctrl_init(void) ifc_ctrl->regs = IFC_BASE_ADDR; /* clear event registers */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); - out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); /* Enable error and event for any detected errors */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, - IFC_NAND_EVTER_EN_OPC_EN | - IFC_NAND_EVTER_EN_PGRDCMPL_EN | - IFC_NAND_EVTER_EN_FTOER_EN | - IFC_NAND_EVTER_EN_WPER_EN); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); - out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); } static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) @@ -810,50 +811,50 @@ static void fsl_ifc_sram_init(void) cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ - csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); - csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); /* chage PageSize 8K and SpareSize 1K*/ csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); /* READID */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, 0x0); - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0); /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, 0x0); - out_be32(&ifc->ifc_nand.col0, 0x0); + ifc_out32(&ifc->ifc_nand.row0, 0x0); + ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -883,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { phys_addr_t phys_addr = virt_to_phys(addr); - cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); - csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { @@ -1004,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->ecc.mode = NAND_ECC_SOFT; } - ver = in_be32(&ifc_ctrl->regs->ifc_rev); + ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); if (ver == FSL_IFC_V1_1_0) fsl_ifc_sram_init(); diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 6b43496..2f82f7c 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) bufnum_end = bufnum + bufperpage - 1; do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); + status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); } while (!(status & IFC_NAND_EVTER_STAT_OPC)); if (status & IFC_NAND_EVTER_STAT_FTOER) { @@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) } for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = bufnum; i <= bufnum_end; i++) { if (check_read_ecc(buf, eccstat, i, page_size)) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); } static inline int bad_block(uchar *marker, int port_size) @@ -140,38 +140,38 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) blk_size = pages_per_blk * page_size; /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); /* Program FIR/FCR for Large/Small page */ if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); /* Read and copy u-boot on SDRAM from NAND device, In parallel * check for Bad block if found skip it and read continue to @@ -184,11 +184,11 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) bufnum = pg_no & bufnum_mask; sram_addr = bufnum * page_size * 2; - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); + ifc_out32(&ifc->ifc_nand.row0, pg_no); + ifc_out32(&ifc->ifc_nand.col0, 0); /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for read to complete */ nand_wait(&buf[sram_addr], bufnum, page_size); diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 0ffd59d..42e208c 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -259,6 +259,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4..c45593b 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,7 +17,75 @@ #include #include "designware.h" -static int configure_phy(struct eth_device *dev); +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -1; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -1; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} static void tx_descs_init(struct eth_device *dev) { @@ -51,7 +119,13 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; } static void rx_descs_init(struct eth_device *dev) @@ -63,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -78,56 +161,68 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + priv->rx_currdescnum = 0; } -static void descs_init(struct eth_device *dev) +static int dw_write_hwaddr(struct eth_device *dev) { - tx_descs_init(dev); - rx_descs_init(dev); + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; } -static int mac_reset(struct eth_device *dev) +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; - ulong start; - int timeout = CONFIG_MACRESET_TIMEOUT; + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } - writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; - if (priv->interface != PHY_INTERFACE_MODE_RGMII) - writel(MII_PORTSELECT, &mac_p->conf); + if (phydev->speed == 100) + conf |= FES_100; - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; + if (phydev->duplex) + conf |= FULLDPLXMODE; - /* Try again after 10usec */ - udelay(10); - }; + writel(conf, &mac_p->conf); - return -1; + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } -static int dw_write_hwaddr(struct eth_device *dev) +static void dw_eth_halt(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; - - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); + struct eth_dma_regs *dma_p = priv->dma_regs_p; - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); - return 0; + phy_shutdown(priv->phydev); } static int dw_eth_init(struct eth_device *dev, bd_t *bis) @@ -135,55 +230,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; - if (priv->phy_configured != 1) - configure_phy(dev); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) + return -1; - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + mdelay(100); + }; - /* Resore the HW MAC address as it has been lost during MAC reset */ + /* Soft reset above clears HW address registers. + * So we have to set it here once again */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); - - writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | - TXSECONDFRAME, &dma_p->opmode); + rx_descs_init(dev); + tx_descs_init(dev); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - if (priv->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); - if ((priv->interface != PHY_INTERFACE_MODE_MII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - if (priv->speed == 100) - conf |= FES_100; + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; } - if (priv->duplex == FULL) - conf |= FULLDPLXMODE; - - writel(conf, &mac_p->conf); - - descs_init(dev); + dw_adjust_link(mac_p, priv->phydev); - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + if (!priv->phydev->link) + return -1; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); @@ -197,6 +280,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + /* Invalidate only "status" field for the following check */ + invalidate_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); @@ -205,6 +293,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) memcpy((void *)desc_p->dmamac_addr, packet, length); + /* Flush data to be sent */ + flush_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + length); + #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ @@ -220,6 +312,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + sizeof(struct dmamacdescr)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -235,18 +331,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) static int dw_eth_recv(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - - u32 status = desc_p->txrx_status; int length = 0; + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + + sizeof(struct dmamacdescr)); + + status = desc_p->txrx_status; + /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ + invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + + length); + NetReceive(desc_p->dmamac_addr, length); /* @@ -255,6 +361,11 @@ static int dw_eth_recv(struct eth_device *dev) */ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + /* Flush only status field - others weren't changed */ + flush_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) desc_num = 0; @@ -265,251 +376,30 @@ static int dw_eth_recv(struct eth_device *dev) return length; } -static void dw_eth_halt(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } - - /* Try again after 10usec */ - udelay(10); - }; - - return -1; -} - -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +static int dw_phy_init(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } + struct phy_device *phydev; + int mask = 0xffffffff; - /* Try again after 10usec */ - udelay(10); - }; - - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); - - return ret; -} - -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) -{ - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; -} +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; #endif -static int dw_reset_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - ulong start; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - - start = get_timer(0); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - - /* Try again after 10usec */ - udelay(10); - }; - - if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) return -1; -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); -#endif - return 0; -} + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; -/* - * Add weak default function for board specific PHY configuration - */ -int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) -{ - return 0; -} - -static int configure_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - ulong start; -#endif - -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else - return -1; -#else - phy_addr = priv->address; -#endif - - /* - * Some boards need board specific PHY initialization. This is - * after the main driver init code but before the auto negotiation - * is run. - */ - if (designware_board_phy_init(dev, phy_addr, - eth_mdio_write, dw_reset_phy) < 0) - return -1; - - if (dw_reset_phy(dev) < 0) - return -1; - -#if defined(CONFIG_DW_AUTONEG) - /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ - eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; - -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - start = get_timer(0); - puts("Waiting for PHY auto negotiation to complete"); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) { - priv->phy_configured = 1; - break; - } + priv->phydev = phydev; + phy_config(phydev); - /* Print dot all 1s to show progress */ - if ((get_timer(start) % 1000) == 0) - putc('.'); - - /* Try again after 1msec */ - udelay(1000); - }; - - if (!(bmsr & BMSR_ANEGCOMPLETE)) - puts(" TIMEOUT!\n"); - else - puts(" done\n"); -#else - priv->phy_configured = 1; -#endif - - priv->speed = miiphy_speed(dev->name, phy_addr); - priv->duplex = miiphy_duplex(dev->name, phy_addr); - - return 0; -} - -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); - - return 0; -} - -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; + return 1; } -#endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -531,19 +421,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - priv->phy_configured = 0; - priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -553,8 +438,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); -#endif - return 1; + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(dev); } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 5440c92..afeacce 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,8 +16,6 @@ #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -217,14 +215,9 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 address; u32 interface; - u32 speed; - u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; - u32 phy_configured; - u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -236,15 +229,8 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; }; -/* Speed specific definitions */ -#define SPEED_10M 1 -#define SPEED_100M 2 -#define SPEED_1000M 3 - -/* Duplex mode specific definitions */ -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 - #endif diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 83cf081..bcc871d 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -12,5 +12,61 @@ phy_interface_t fman_port_enet_if(enum fm_port port) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + return PHY_INTERFACE_MODE_NONE; } diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index bb5044b..262b67b 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -261,6 +261,10 @@ static int setup_phy(struct eth_device *dev) phydev->dev->name); return 0; } + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } switch (phydev->speed) { case 1000: diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 6a017a8..381bca4 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -339,6 +339,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_config(phydev); phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + switch (phydev->speed) { case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 2085cd6..6317fb1 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -510,8 +510,8 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); - printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, - pci_info->regs); + printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, + (temp16 & 0xf), pci_info->regs); hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6b4cade..5eb4601 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o +obj-$(CONFIG_ARC_SERIAL) += serial_arc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 8de2eca..d4ed60c 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -17,62 +18,34 @@ DECLARE_GLOBAL_DATA_PTR; static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF assignment*/ - static void oc_serial_setbrg(void) { int n, k; const unsigned max_uns = 0xFFFFFFFF; unsigned best_n, best_m, baud; + unsigned baudrate; - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - (unsigned)CONFIG_BAUDRATE) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) - break; - } - best_m = - ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(baud, &uart->baud); - - return; -} - +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + /* Everything's already setup for fixed-baud PTF assignment */ + baudrate = CONFIG_BAUDRATE; #else - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - + baudrate = gd->baudrate; +#endif /* compute best N and M couple */ best_n = YANU_MAX_PRESCALER_N; for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - gd->baudrate) { + baudrate) { best_n = n; break; } } for (k = 0;; k++) { - if (gd->baudrate <= (max_uns >> (15+n-k))) + if (baudrate <= (max_uns >> (15+n-k))) break; } best_m = - (gd->baudrate * (1 << (15 + n - k))) / + (baudrate * (1 << (15 + n - k))) / ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; @@ -81,9 +54,6 @@ static void oc_serial_setbrg(void) return; } - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - static int oc_serial_init(void) { unsigned action,control; @@ -154,7 +124,7 @@ static int oc_serial_tstc(void) ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); } -statoc int oc_serial_getc(void) +static int oc_serial_getc(void) { while (serial_tstc() == 0) WATCHDOG_RESET (); diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df2b84a..05cb369 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); +serial_initfunc(arc_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -253,6 +254,7 @@ void serial_initialize(void) sh_serial_initialize(); arm_dcc_initialize(); mxs_auart_initialize(); + arc_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c new file mode 100644 index 0000000..e63d25d --- /dev/null +++ b/drivers/serial/serial_arc.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct arc_serial_regs { + unsigned int id0; + unsigned int id1; + unsigned int id2; + unsigned int id3; + unsigned int data; + unsigned int status; + unsigned int baudl; + unsigned int baudh; +}; + +/* Bit definitions of STATUS register */ +#define UART_RXEMPTY (1 << 5) +#define UART_OVERFLOW_ERR (1 << 1) +#define UART_TXEMPTY (1 << 7) + +struct arc_serial_regs *regs; + +static void arc_serial_setbrg(void) +{ + int arc_console_baud; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; + writel(arc_console_baud & 0xff, ®s->baudl); + writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); +} + +static int arc_serial_init(void) +{ + regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; + serial_setbrg(); + return 0; +} + +static void arc_serial_putc(const char c) +{ + if (c == '\n') + arc_serial_putc('\r'); + + while (!(readl(®s->status) & UART_TXEMPTY)) + ; + + writel(c, ®s->data); +} + +static int arc_serial_tstc(void) +{ + return !(readl(®s->status) & UART_RXEMPTY); +} + +static int arc_serial_getc(void) +{ + while (!arc_serial_tstc()) + ; + + /* Check for overflow errors */ + if (readl(®s->status) & UART_OVERFLOW_ERR) + return 0; + + return readl(®s->data) & 0xFF; +} + +static void arc_serial_puts(const char *s) +{ + while (*s) + arc_serial_putc(*s++); +} + +static struct serial_device arc_serial_drv = { + .name = "arc_serial", + .start = arc_serial_init, + .stop = NULL, + .setbrg = arc_serial_setbrg, + .putc = arc_serial_putc, + .puts = arc_serial_puts, + .getc = arc_serial_getc, + .tstc = arc_serial_tstc, +}; + +void arc_serial_initialize(void) +{ + serial_register(&arc_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &arc_serial_drv; +} diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index e613994..988438e 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -18,10 +18,14 @@ #define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ #define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define ULITE_CONTROL_RST_TX 0x01 +#define ULITE_CONTROL_RST_RX 0x02 + struct uartlite { unsigned int rx_fifo; unsigned int tx_fifo; unsigned int status; + unsigned int control; }; static struct uartlite *userial_ports[4] = { @@ -75,8 +79,16 @@ static int uartlite_serial_tstc(const int port) static int uartlite_serial_init(const int port) { - if (userial_ports[port]) + struct uartlite *regs = userial_ports[port]; + + if (regs) { + out_be32(®s->control, 0); + out_be32(®s->control, + ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); return 0; + } + return -1; } diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 819dec6..21a3ef4 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -20,8 +20,8 @@ #include #elif defined(CONFIG_DW_UDC) #include -#elif defined(CONFIG_MV_UDC) -#include +#elif defined(CONFIG_CI_UDC) +#include #endif #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index f13b172..804a2bd 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -21,7 +21,7 @@ endif ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o -obj-$(CONFIG_MV_UDC) += mv_udc.o +obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/ci_udc.c similarity index 79% rename from drivers/usb/gadget/mv_udc.c rename to drivers/usb/gadget/ci_udc.c index da41738..14b1e9b 100644 --- a/drivers/usb/gadget/mv_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -20,9 +20,9 @@ #include #include #include -#include +#include #include "../host/ehci.h" -#include "mv_udc.h" +#include "ci_udc.h" /* * Check if the system has too long cachelines. If the cachelines are @@ -70,85 +70,85 @@ static struct usb_endpoint_descriptor ep0_in_desc = { .bmAttributes = USB_ENDPOINT_XFER_CONTROL, }; -static int mv_pullup(struct usb_gadget *gadget, int is_on); -static int mv_ep_enable(struct usb_ep *ep, +static int ci_pullup(struct usb_gadget *gadget, int is_on); +static int ci_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc); -static int mv_ep_disable(struct usb_ep *ep); -static int mv_ep_queue(struct usb_ep *ep, +static int ci_ep_disable(struct usb_ep *ep); +static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req); +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); -static struct usb_gadget_ops mv_udc_ops = { - .pullup = mv_pullup, +static struct usb_gadget_ops ci_udc_ops = { + .pullup = ci_pullup, }; -static struct usb_ep_ops mv_ep_ops = { - .enable = mv_ep_enable, - .disable = mv_ep_disable, - .queue = mv_ep_queue, - .alloc_request = mv_ep_alloc_request, - .free_request = mv_ep_free_request, +static struct usb_ep_ops ci_ep_ops = { + .enable = ci_ep_enable, + .disable = ci_ep_disable, + .queue = ci_ep_queue, + .alloc_request = ci_ep_alloc_request, + .free_request = ci_ep_free_request, }; /* Init values for USB endpoints. */ -static const struct usb_ep mv_ep_init[2] = { +static const struct usb_ep ci_ep_init[2] = { [0] = { /* EP 0 */ .maxpacket = 64, .name = "ep0", - .ops = &mv_ep_ops, + .ops = &ci_ep_ops, }, [1] = { /* EP 1..n */ .maxpacket = 512, .name = "ep-", - .ops = &mv_ep_ops, + .ops = &ci_ep_ops, }, }; -static struct mv_drv controller = { +static struct ci_drv controller = { .gadget = { - .name = "mv_udc", - .ops = &mv_udc_ops, + .name = "ci_udc", + .ops = &ci_udc_ops, .is_dualspeed = 1, }, }; /** - * mv_get_qh() - return queue head for endpoint + * ci_get_qh() - return queue head for endpoint * @ep_num: Endpoint number * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) * * This function returns the QH associated with particular endpoint * and it's direction. */ -static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) +static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) { return &controller.epts[(ep_num * 2) + dir_in]; } /** - * mv_get_qtd() - return queue item for endpoint + * ci_get_qtd() - return queue item for endpoint * @ep_num: Endpoint number * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) * * This function returns the QH associated with particular endpoint * and it's direction. */ -static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) +static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) { return controller.items[(ep_num * 2) + dir_in]; } /** - * mv_flush_qh - flush cache over queue head + * ci_flush_qh - flush cache over queue head * @ep_num: Endpoint number * * This function flushes cache over QH for particular endpoint. */ -static void mv_flush_qh(int ep_num) +static void ci_flush_qh(int ep_num) { - struct ept_queue_head *head = mv_get_qh(ep_num, 0); + struct ept_queue_head *head = ci_get_qh(ep_num, 0); const uint32_t start = (uint32_t)head; const uint32_t end = start + 2 * sizeof(*head); @@ -156,14 +156,14 @@ static void mv_flush_qh(int ep_num) } /** - * mv_invalidate_qh - invalidate cache over queue head + * ci_invalidate_qh - invalidate cache over queue head * @ep_num: Endpoint number * * This function invalidates cache over QH for particular endpoint. */ -static void mv_invalidate_qh(int ep_num) +static void ci_invalidate_qh(int ep_num) { - struct ept_queue_head *head = mv_get_qh(ep_num, 0); + struct ept_queue_head *head = ci_get_qh(ep_num, 0); uint32_t start = (uint32_t)head; uint32_t end = start + 2 * sizeof(*head); @@ -171,14 +171,14 @@ static void mv_invalidate_qh(int ep_num) } /** - * mv_flush_qtd - flush cache over queue item + * ci_flush_qtd - flush cache over queue item * @ep_num: Endpoint number * * This function flushes cache over qTD pair for particular endpoint. */ -static void mv_flush_qtd(int ep_num) +static void ci_flush_qtd(int ep_num) { - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; const uint32_t end_raw = start + 2 * sizeof(*item); const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); @@ -187,14 +187,14 @@ static void mv_flush_qtd(int ep_num) } /** - * mv_invalidate_qtd - invalidate cache over queue item + * ci_invalidate_qtd - invalidate cache over queue item * @ep_num: Endpoint number * * This function invalidates cache over qTD pair for particular endpoint. */ -static void mv_invalidate_qtd(int ep_num) +static void ci_invalidate_qtd(int ep_num) { - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; const uint32_t end_raw = start + 2 * sizeof(*item); const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); @@ -203,20 +203,20 @@ static void mv_invalidate_qtd(int ep_num) } static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - return &mv_ep->req; + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + return &ci_ep->req; } -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) { return; } static void ep_enable(int num, int in, int maxpacket) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; unsigned n; n = readl(&udc->epctrl[num]); @@ -226,22 +226,22 @@ static void ep_enable(int num, int in, int maxpacket) n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); if (num != 0) { - struct ept_queue_head *head = mv_get_qh(num, in); + struct ept_queue_head *head = ci_get_qh(num, in); head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; - mv_flush_qh(num); + ci_flush_qh(num); } writel(n, &udc->epctrl[num]); } -static int mv_ep_enable(struct usb_ep *ep, +static int ci_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); int num, in; num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (desc->bEndpointAddress & USB_DIR_IN) != 0; - mv_ep->desc = desc; + ci_ep->desc = desc; if (num) { int max = get_unaligned_le16(&desc->wMaxPacketSize); @@ -259,15 +259,15 @@ static int mv_ep_enable(struct usb_ep *ep, return 0; } -static int mv_ep_disable(struct usb_ep *ep) +static int ci_ep_disable(struct usb_ep *ep) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); - mv_ep->desc = NULL; + ci_ep->desc = NULL; return 0; } -static int mv_bounce(struct mv_ep *ep, int in) +static int ci_bounce(struct ci_ep *ep, int in) { uint32_t addr = (uint32_t)ep->req.buf; uint32_t ba; @@ -306,7 +306,7 @@ flush: return 0; } -static void mv_debounce(struct mv_ep *ep, int in) +static void ci_debounce(struct ci_ep *ep, int in) { uint32_t addr = (uint32_t)ep->req.buf; uint32_t ba = (uint32_t)ep->b_buf; @@ -328,36 +328,36 @@ free: free(ep->b_buf); } -static int mv_ep_queue(struct usb_ep *ep, +static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_item *item; struct ept_queue_head *head; int bit, num, len, in, ret; - num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = mv_get_qtd(num, in); - head = mv_get_qh(num, in); + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + head = ci_get_qh(num, in); len = req->length; - ret = mv_bounce(mv_ep, in); + ret = ci_bounce(ci_ep, in); if (ret) return ret; item->next = TERMINATE; item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)mv_ep->b_buf; - item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; - mv_flush_qtd(num); + item->page0 = (uint32_t)ci_ep->b_buf; + item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; + ci_flush_qtd(num); head->next = (unsigned) item; head->info = 0; DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, mv_ep->b_buf); - mv_flush_qh(num); + num, in ? "in" : "out", len, ci_ep->b_buf); + ci_flush_qh(num); if (in) bit = EPT_TX(num); @@ -369,7 +369,7 @@ static int mv_ep_queue(struct usb_ep *ep, return 0; } -static void handle_ep_complete(struct mv_ep *ep) +static void handle_ep_complete(struct ci_ep *ep) { struct ept_queue_item *item; int num, in, len; @@ -377,8 +377,8 @@ static void handle_ep_complete(struct mv_ep *ep) in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) ep->desc = &ep0_out_desc; - item = mv_get_qtd(num, in); - mv_invalidate_qtd(num); + item = ci_get_qtd(num, in); + ci_invalidate_qtd(num); if (item->info & 0xff) printf("EP%d/%s FAIL info=%x pg0=%x\n", @@ -386,7 +386,7 @@ static void handle_ep_complete(struct mv_ep *ep) len = (item->info >> 16) & 0x7fff; ep->req.length -= len; - mv_debounce(ep, in); + ci_debounce(ep, in); DBG("ept%d %s complete %x\n", num, in ? "in" : "out", len); @@ -403,15 +403,15 @@ static void handle_ep_complete(struct mv_ep *ep) static void handle_setup(void) { struct usb_request *req = &controller.ep[0].req; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_head *head; struct usb_ctrlrequest r; int status = 0; int num, in, _num, _in, i; char *buf; - head = mv_get_qh(0, 0); /* EP0 OUT */ + head = ci_get_qh(0, 0); /* EP0 OUT */ - mv_invalidate_qh(0); + ci_invalidate_qh(0); memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); writel(EPT_RX(0), &udc->epstat); DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), @@ -425,7 +425,7 @@ static void handle_setup(void) if ((r.wValue == 0) && (r.wLength == 0)) { req->length = 0; for (i = 0; i < NUM_ENDPOINTS; i++) { - struct mv_ep *ep = &controller.ep[i]; + struct ci_ep *ep = &controller.ep[i]; if (!ep->desc) continue; @@ -478,7 +478,7 @@ static void stop_activity(void) { int i, num, in; struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; writel(readl(&udc->epcomp), &udc->epcomp); writel(readl(&udc->epstat), &udc->epstat); writel(0xffffffff, &udc->epflush); @@ -492,16 +492,16 @@ static void stop_activity(void) & USB_ENDPOINT_NUMBER_MASK; in = (controller.ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0; - head = mv_get_qh(num, in); + head = ci_get_qh(num, in); head->info = INFO_ACTIVE; - mv_flush_qh(num); + ci_flush_qh(num); } } } void udc_irq(void) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; unsigned n = readl(&udc->usbsts); writel(n, &udc->usbsts); int bit, i, num, in; @@ -563,7 +563,7 @@ void udc_irq(void) int usb_gadget_handle_interrupts(void) { u32 value; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; value = readl(&udc->usbsts); if (value) @@ -572,9 +572,9 @@ int usb_gadget_handle_interrupts(void) return value; } -static int mv_pullup(struct usb_gadget *gadget, int is_on) +static int ci_pullup(struct usb_gadget *gadget, int is_on) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; if (is_on) { /* RESET */ writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); @@ -602,7 +602,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on) void udc_disconnect(void) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* disable pullup */ stop_activity(); writel(USBCMD_FS2, &udc->usbcmd); @@ -611,7 +611,7 @@ void udc_disconnect(void) controller.driver->disconnect(&controller.gadget); } -static int mvudc_probe(void) +static int ci_udc_probe(void) { struct ept_queue_head *head; uint8_t *imem; @@ -673,23 +673,23 @@ static int mvudc_probe(void) controller.items[i] = (struct ept_queue_item *)imem; if (i & 1) { - mv_flush_qh(i - 1); - mv_flush_qtd(i - 1); + ci_flush_qh(i - 1); + ci_flush_qtd(i - 1); } } INIT_LIST_HEAD(&controller.gadget.ep_list); /* Init EP 0 */ - memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); + memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); controller.ep[0].desc = &ep0_in_desc; controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); /* Init EP 1..n */ for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &mv_ep_init[1], - sizeof(*mv_ep_init)); + memcpy(&controller.ep[i].ep, &ci_ep_init[1], + sizeof(*ci_ep_init)); list_add_tail(&controller.ep[i].ep.ep_list, &controller.gadget.ep_list); } @@ -699,7 +699,7 @@ static int mvudc_probe(void) int usb_gadget_register_driver(struct usb_gadget_driver *driver) { - struct mv_udc *udc; + struct ci_udc *udc; int ret; if (!driver) @@ -713,9 +713,9 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) if (ret) return ret; - ret = mvudc_probe(); + ret = ci_udc_probe(); if (!ret) { - udc = (struct mv_udc *)controller.ctrl->hcor; + udc = (struct ci_udc *)controller.ctrl->hcor; /* select ULPI phy */ writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); diff --git a/drivers/usb/gadget/mv_udc.h b/drivers/usb/gadget/ci_udc.h similarity index 94% rename from drivers/usb/gadget/mv_udc.h rename to drivers/usb/gadget/ci_udc.h index c7d8b33..42f6ef4 100644 --- a/drivers/usb/gadget/mv_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -3,12 +3,12 @@ * * Licensed under the GPL-2 or later. */ -#ifndef __GADGET__MV_UDC_H__ -#define __GADGET__MV_UDC_H__ +#ifndef __GADGET__CI_UDC_H__ +#define __GADGET__CI_UDC_H__ #define NUM_ENDPOINTS 6 -struct mv_udc { +struct ci_udc { #define MICRO_8FRAME 0x8 #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) #define USBCMD_FS2 (1 << 15) @@ -48,7 +48,7 @@ struct mv_udc { u32 epctrl[16]; /* 0x1c0 */ }; -struct mv_ep { +struct ci_ep { struct usb_ep ep; struct list_head queue; const struct usb_endpoint_descriptor *desc; @@ -59,14 +59,14 @@ struct mv_ep { uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); }; -struct mv_drv { +struct ci_drv { struct usb_gadget gadget; struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; struct ept_queue_item *items[2 * NUM_ENDPOINTS]; uint8_t *items_mem; - struct mv_ep ep[NUM_ENDPOINTS]; + struct ci_ep ep[NUM_ENDPOINTS]; }; struct ept_queue_head { diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index b1fe8bd..f896169 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2515,7 +2515,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, buffhds_first_it: bh->inreq_busy = 0; bh->outreq_busy = 0; - bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL); + bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN); if (unlikely(!bh->buf)) { rc = -ENOMEM; goto error_release; @@ -2622,7 +2622,7 @@ usb_copy_descriptors(struct usb_descriptor_header **src) bytes += (*tmp)->bLength; bytes += (n_desc + 1) * sizeof(*tmp); - mem = kmalloc(bytes, GFP_KERNEL); + mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes); if (!mem) return NULL; diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c4c9909..f5c0224 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -614,7 +614,7 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) { struct usb_request *req; - req = alloc_ep_req(ep, ep->maxpacket); + req = alloc_ep_req(ep, THOR_PACKET_SIZE); debug("%s: ep:%p req:%p\n", __func__, ep, req); if (!req) @@ -623,8 +623,6 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) memset(req->buf, 0, req->length); req->complete = thor_rx_tx_complete; - memset(req->buf, 0x55, req->length); - return req; } diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index aa54b85..cc94771 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,10 +144,10 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_MV_UDC -#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) +#ifdef CONFIG_CI_UDC +#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name)) #else -#define gadget_is_mv(g) 0 +#define gadget_is_ci(g) 0 #endif #ifdef CONFIG_USB_GADGET_FOTG210 @@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x19; else if (gadget_is_m66592(gadget)) return 0x20; - else if (gadget_is_mv(gadget)) + else if (gadget_is_ci(gadget)) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index ba17a04..63d4487 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -843,7 +843,7 @@ static struct s3c_udc memory = { int s3c_udc_probe(struct s3c_plat_otg_data *pdata) { struct s3c_udc *dev = &memory; - int retval = 0, i; + int retval = 0; debug("%s: %p\n", __func__, pdata); @@ -864,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) the_controller = dev; - for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) { - dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE, - DMA_BUFFER_SIZE); - dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i]; - invalidate_dcache_range((unsigned long) dev->dma_buf[i], - (unsigned long) (dev->dma_buf[i] - + DMA_BUFFER_SIZE)); + usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, + ROUND(sizeof(struct usb_ctrlrequest), + CONFIG_SYS_CACHELINE_SIZE)); + if (!usb_ctrl) { + error("No memory available for UDC!\n"); + return -ENOMEM; } - usb_ctrl = dev->dma_buf[0]; - usb_ctrl_dma_addr = dev->dma_addr[0]; + + usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; udc_reinit(dev); diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 1cbf8f6..06dfeed 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -29,10 +29,6 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) { u32 ep_ctrl; - flush_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); @@ -52,10 +48,6 @@ void s3c_udc_pre_setup(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -82,10 +74,6 @@ static inline void s3c_ep0_complete_out(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Complete Out packet.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -109,27 +97,20 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) u32 ep_num = ep_index(ep); buf = req->req.buf + req->req.actual; - - length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket); + length = min(req->req.length - req->req.actual, + ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); ep->len = length; ep->dma_buf = buf; - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num], - (unsigned long) ep->dev->dma_buf[ep_num] - + ROUND(ep->ep.maxpacket, - CONFIG_SYS_CACHELINE_SIZE)); - - if (length == 0) + if (ep_num == EP0_CON || length == 0) pktcnt = 1; else pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; - pktcnt = 1; ctrl = readl(®->out_endp[ep_num].doepctl); - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->out_endp[ep_num].doepdma); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -152,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) u32 *buf, ctrl = 0; u32 length, pktcnt; u32 ep_num = ep_index(ep); - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; buf = req->req.buf + req->req.actual; length = req->req.length - req->req.actual; @@ -162,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - memcpy(p, ep->dma_buf, length); - flush_dcache_range((unsigned long) p , - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); if (length == 0) pktcnt = 1; @@ -178,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->in_endp[ep_num].diepdma); + writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -212,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) struct s3c_ep *ep = &dev->ep[ep_num]; struct s3c_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; if (list_empty(&ep->queue)) { debug_cond(DEBUG_OUT_EP != 0, @@ -232,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) xfer_size = ep->len - xfer_size; - invalidate_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); - - memcpy(ep->dma_buf, p, ep->len); + /* + * NOTE: + * + * Please be careful with proper buffer allocation for USB request, + * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only + * with starting address, but also its size shall be a cache line + * multiplication. + * + * This will prevent from corruption of data allocated immediatelly + * before or after the buffer. + * + * For armv7, the cache_v7.c provides proper code to emit "ERROR" + * message to warn users. + */ + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); req->req.actual += min(xfer_size, req->req.length - req->req.actual); is_short = (xfer_size < ep->ep.maxpacket); @@ -729,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) { - u32 bytes; - - bytes = sizeof(struct usb_ctrlrequest); - - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)], - (unsigned long) ep->dev->dma_buf[ep_index(ep)] - + DMA_BUFFER_SIZE); + invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); debug_cond(DEBUG_EP0 != 0, - "%s: bytes=%d, ep_index=%d %p\n", __func__, - bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]); + "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, + max, ep_index(ep), cp); - return bytes; + return max; } /** @@ -873,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -u16 g_status; - int s3c_udc_get_status(struct s3c_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; + u16 g_status = 0; u32 ep_ctrl; - u32 *p = the_controller->dma_buf[1]; debug_cond(DEBUG_SETUP != 0, "%s: *** USB_REQ_GET_STATUS\n", __func__); @@ -918,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 1; } - memcpy(p, &g_status, sizeof(g_status)); + memcpy(usb_ctrl, &g_status, sizeof(g_status)); - flush_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) usb_ctrl, + (unsigned long) usb_ctrl + + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma); + writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 32a19ce..c5c025d 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -210,6 +210,19 @@ gd_t *global_data; " l.jr r13\n" \ " l.nop\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13"); +#elif defined(CONFIG_ARC) +/* + * r25 holds the pointer to the global_data. r10 is call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile( \ +" .align 4\n" \ +" .globl " #x "\n" \ +#x ":\n" \ +" ld r10, [r25, %0]\n" \ +" ld r10, [r10, %1]\n" \ +" j [r10]\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10"); #else /*" addi $sp, $sp, -24\n" \ " br $r16\n" \*/ diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 0000000..df4570c --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/common.h b/include/common.h index d5ebb25..221b776 100644 --- a/include/common.h +++ b/include/common.h @@ -408,6 +408,9 @@ static inline int setenv_addr(const char *varname, const void *addr) #ifdef CONFIG_MIPS # include #endif /* CONFIG_MIPS */ +#ifdef CONFIG_ARC +# include +#endif /* CONFIG_ARC */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d847069..3e8983f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h new file mode 100644 index 0000000..5d18a4b --- /dev/null +++ b/include/config_distro_defaults.h @@ -0,0 +1,56 @@ +/* + * Copyright 2013-2014 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H +#define _CONFIG_CMD_DISTRO_DEFAULTS_H + +/* + * List of all commands and options that when defined enables support for + * features required by distros to support boards in a standardised and + * consitant manner. + */ + +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK + +#if defined(__arm__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#else +#define CONFIG_BOOTP_VCI_STRING "U-boot.arm" +#endif +#endif + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_PXE + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 2 +#define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SYS_HUSH_PARSER + +#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8234a82..75ea125 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 5e988c2..7cfda50 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -386,6 +383,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -543,13 +544,12 @@ #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -627,9 +627,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index aafa813..ed9ca8a 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -394,6 +391,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -551,8 +552,11 @@ #endif #ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 + #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -631,9 +635,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h new file mode 100644 index 0000000..88d27db --- /dev/null +++ b/include/configs/arcangel4-be.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_SYS_BIG_ENDIAN +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h new file mode 100644 index 0000000..4579eb9 --- /dev/null +++ b/include/configs/arcangel4.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/axs101.h b/include/configs/axs101.h new file mode 100644 index 0000000..af2e63b --- /dev/null +++ b/include/configs/axs101.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_AXS101_H_ +#define _CONFIG_AXS101_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CLK_FREQ 750000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* dwgmac doesn't work with D$ enabled now */ +#define CONFIG_SYS_DCACHE_OFF + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * UART configuration + * + * CONFIG_CONS_INDEX = 1 - Debug UART + * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB + */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#if (CONFIG_CONS_INDEX == 1) + /* Debug UART */ +# define CONFIG_SYS_NS16550_CLK 33333000 +#else + /* FPGA UARTs use different clock */ +# define CONFIG_SYS_NS16550_CLK 33333333 +#endif +#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) +#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) +#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) +#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_ENV_EEPROM_BUS 2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_BASE 0xE001D000 +#define CONFIG_SYS_I2C_BASE1 0xE001E000 +#define CONFIG_SYS_I2C_BASE2 0xE001F000 +#define CONFIG_SYS_I2C_BUS_MAX 3 +#define IC_CLK 50 + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 + +/* + * SD/MMC configuration + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_DOS_PARTITION + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_MII +#define CONFIG_PHY_GIGE + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "axs# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_AXS101_H_ */ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b..12192ff 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,12 +72,13 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 04ae3ca..86574c8 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -73,6 +73,8 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SUPPORT_EMMC_BOOT + /* USB xHCI HOST */ #define CONFIG_CMD_USB #define CONFIG_USB_HOST diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 7361072..517f46a 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -99,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -111,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 569b574..0d24f78 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -15,6 +15,10 @@ #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + #define CONFIG_NAND_ECC_BCH /* common KM defines */ @@ -148,8 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ -#define CONFIG_BOOTCOUNT_LIMIT - /* * Local Bus Definitions */ @@ -206,8 +208,13 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ +/* bootcounter in QRIO */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT @@ -263,7 +270,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ /* I2C */ + #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ @@ -276,6 +286,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ @@ -286,6 +302,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 4158c8d..8bb3571 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -13,6 +13,11 @@ #define CONFIG_HOSTNAME kmlion1 #define CONFIG_KM_BOARD_NAME "kmlion1" +/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + #else #error ("Board not supported") #endif @@ -42,6 +47,7 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM /* Local bus app1 Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif /* App2 Local bus */ #define CONFIG_SYS_LBAPP2_BASE 0xE0000000 @@ -63,6 +69,5 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM /* Local bus app2 Options */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index aa8d59d..486787e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -200,7 +200,8 @@ # define CONFIG_SYS_MAX_FLASH_SECT 512 /* hardware flash protection */ # define CONFIG_SYS_FLASH_PROTECTION - +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # ifdef RAMENV # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 @@ -446,4 +447,64 @@ # undef CONFIG_PHYLIB #endif +/* SPL part */ +#define CONFIG_SPL +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_NOR_SUPPORT + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x60000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x40000) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 + +/* + * The main reason to do it in this way is that MALLOC_START + * can't be defined - common/spl/spl.c + */ +#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) +# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START +#else +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END +#endif + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SPL_STACK_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd..e44ec88 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -#define CONFIG_MV_UDC +#define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 51dff23..783b7c3 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,6 +37,7 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART #define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index a85eb1c..8cce34a 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -56,7 +56,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 23f7ad7..e090a37 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc58..28dddcc 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/configs/x600.h b/include/configs/x600.h index 39540e3..00b938a 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -74,10 +74,9 @@ /* Ethernet config options */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 022bc95..8e6b365 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -55,7 +55,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67..b641558 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,7 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac { diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index be6c107..58a6efd 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,20 @@ #include #include + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + /* * CSPR - Chip Select Property Register */ @@ -773,20 +787,22 @@ extern void init_early_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, diff --git a/include/image.h b/include/image.h index 7de2bb2..3ba8c2e 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ struct lmb; #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ #define IH_ARCH_ARM64 22 /* ARM64 */ +#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ /* * Image Types diff --git a/include/mmc.h b/include/mmc.h index e1060b9..e95a237 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -187,6 +187,9 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -310,8 +313,10 @@ int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -/* Function to send commands to open/close the specified boot partition */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /** * Start device initialization and return immediately; it does not block on diff --git a/include/netdev.h b/include/netdev.h index 47fa80d..3705629 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); +int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); diff --git a/include/spl.h b/include/spl.h index 5e24856..dad00c0 100644 --- a/include/spl.h +++ b/include/spl.h @@ -16,6 +16,7 @@ #define MMCSD_MODE_UNDEFINED 0 #define MMCSD_MODE_RAW 1 #define MMCSD_MODE_FAT 2 +#define MMCSD_MODE_EMMCBOOT 3 struct spl_image_info { const char *name; diff --git a/include/usb/mv_udc.h b/include/usb/ci_udc.h similarity index 73% rename from include/usb/mv_udc.h rename to include/usb/ci_udc.h index f6c7b5e..0dee504 100644 --- a/include/usb/mv_udc.h +++ b/include/usb/ci_udc.h @@ -6,9 +6,9 @@ */ -#ifndef __MV_UDC_H__ -#define __MV_UDC_H__ +#ifndef __CI_UDC_H__ +#define __CI_UDC_H__ #define EP_MAX_PACKET_SIZE 0x200 #define EP0_MAX_PACKET_SIZE 64 -#endif /* __MV_UDC_H__ */ +#endif /* __CI_UDC_H__ */ diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 734c6cd..ce3dd2c 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -10,6 +10,7 @@ #define __S3C_USB_GADGET #include +#include #include #include #include @@ -19,7 +20,7 @@ /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (4096*4) +#define DMA_BUFFER_SIZE (16*SZ_1K) #define EP0_FIFO_SIZE 64 #define EP_FIFO_SIZE 512 @@ -81,9 +82,6 @@ struct s3c_udc { struct s3c_plat_otg_data *pdata; - void *dma_buf[S3C_MAX_ENDPOINTS+1]; - dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1]; - int ep0state; struct s3c_ep ep[S3C_MAX_ENDPOINTS]; diff --git a/include/zynqpl.h b/include/zynqpl.h index 6107cbf..c81446e 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); extern int zynq_info(Xilinx_desc *desc); #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_7045 0x11 @@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc); /* Device Image Sizes */ #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z045_SIZE 106571232/8 @@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc); #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } +#define XILINX_XC7Z015_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" } + #define XILINX_XC7Z020_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } diff --git a/net/eth.c b/net/eth.c index c96e767..32bd10c 100644 --- a/net/eth.c +++ b/net/eth.c @@ -279,7 +279,7 @@ int eth_initialize(bd_t *bis) eth_current = NULL; bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif