From: Ingo Molnar <mingo@elte.hu>
Date: Mon, 13 Oct 2008 08:52:30 +0000 (+0200)
Subject: Merge branch 'linus' into oprofile
X-Git-Tag: upstream/snapshot3+hdmi~21831^2~14
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c493756e2a8a78bcaae30668317890dcfe86e7c3;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

Merge branch 'linus' into oprofile

Conflicts:
	arch/x86/kernel/apic_32.c
	include/linux/pci_ids.h
---

c493756e2a8a78bcaae30668317890dcfe86e7c3
diff --cc arch/x86/kernel/apic_32.c
index 0ff576d,a91c57c..21c831d
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@@ -241,6 -291,36 +291,40 @@@ static void __setup_APIC_LVTT(unsigned 
  }
  
  /*
+  * Setup extended LVT, AMD specific (K8, family 10h)
+  *
+  * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
+  * MCE interrupts are supported. Thus MCE offset must be set to 0.
++ *
++ * If mask=1, the LVT entry does not generate interrupts while mask=0
++ * enables the vector. See also the BKDGs.
+  */
+ 
+ #define APIC_EILVT_LVTOFF_MCE 0
+ #define APIC_EILVT_LVTOFF_IBS 1
+ 
+ static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
+ {
+ 	unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
+ 	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
+ 
+ 	apic_write(reg, v);
+ }
+ 
+ u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
+ {
+ 	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
+ 	return APIC_EILVT_LVTOFF_MCE;
+ }
+ 
+ u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
+ {
+ 	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
+ 	return APIC_EILVT_LVTOFF_IBS;
+ }
++EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
+ 
+ /*
   * Program the next event, relative to now
   */
  static int lapic_next_event(unsigned long delta,