From: Evan Cheng Date: Mon, 27 Jul 2009 03:14:20 +0000 (+0000) Subject: Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more... X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c47e109335c0cf6016c756848998a8df580fe84b;p=platform%2Fupstream%2Fllvm.git Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. llvm-svn: 77181 --- diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 059f2bf..2d1a5a8 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -636,7 +636,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (I != MBB.end()) DL = I->getDebugLoc(); if (RC == ARM::GPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STRrr))) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { @@ -659,7 +659,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (I != MBB.end()) DL = I->getDebugLoc(); if (RC == ARM::GPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) @@ -679,7 +679,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned OpNum = Ops[0]; unsigned Opc = MI->getOpcode(); MachineInstr *NewMI = NULL; - if (Opc == getOpcode(ARMII::MOVr)) { + if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { // If it is updating CPSR, then it cannot be folded. if (MI->getOperand(4).getReg() != ARM::CPSR) { unsigned Pred = MI->getOperand(2).getImm(); @@ -688,19 +688,32 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); bool isUndef = MI->getOperand(1).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STRrr))) - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) - .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); + if (Opc == ARM::MOVr) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) + .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); + else // ARM::t2MOVr + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) + .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); bool isUndef = MI->getOperand(0).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDRrr))) - .addReg(DstReg, - RegState::Define | - getDeadRegState(isDead) | - getUndefRegState(isUndef)) - .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); + if (Opc == ARM::MOVr) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) + .addReg(DstReg, + RegState::Define | + getDeadRegState(isDead) | + getUndefRegState(isUndef)) + .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); + else // ARM::t2MOVr + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) + .addReg(DstReg, + RegState::Define | + getDeadRegState(isDead) | + getUndefRegState(isUndef)) + .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } } } @@ -767,7 +780,7 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, if (Ops.size() != 1) return false; unsigned Opc = MI->getOpcode(); - if (Opc == getOpcode(ARMII::MOVr)) { + if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { // If it is updating CPSR, then it cannot be folded. return MI->getOperand(4).getReg() != ARM::CPSR; } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 949bac4..a2bcacc 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -168,10 +168,8 @@ namespace ARMII { B, Bcc, BX_RET, - LDRrr, LDRri, MOVr, - STRrr, STRri, SUBri, SUBrs, @@ -271,6 +269,7 @@ public: unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const; + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 2bd407e..f8c079f 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1305,8 +1305,7 @@ emitPrologue(MachineFunction &MF) const { // Build the new SUBri to adjust SP for integer callee-save spill area 1. emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size); - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr), - getOpcode(ARMII::STRri), 1, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); // Darwin ABI requires FP to point to the stack slot that contains the // previous FP. @@ -1321,8 +1320,7 @@ emitPrologue(MachineFunction &MF) const { emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size); // Build the new SUBri to adjust SP for FP callee-save spill area. - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr), - getOpcode(ARMII::STRri), 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize); // Determine starting offsets of spill areas. @@ -1362,8 +1360,8 @@ static bool isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const unsigned *CSRegs) { return ((MI->getOpcode() == (int)ARM::FLDD || - MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRrr) || - MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRri)) && + MI->getOpcode() == (int)ARM::LDR || + MI->getOpcode() == (int)ARM::t2LDRi12) && MI->getOperand(1).isFI() && isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); } @@ -1428,13 +1426,11 @@ emitEpilogue(MachineFunction &MF, emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize()); // Move SP to start of integer callee save spill area 1. - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr), - getOpcode(ARMII::LDRri), 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size()); // Move SP to SP upon entry to the function. - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr), - getOpcode(ARMII::LDRri), 1, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size()); } diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index 0f649d4..6b638d6 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -71,10 +71,8 @@ getOpcode(ARMII::Op Op) const { case ARMII::B: return ARM::B; case ARMII::Bcc: return ARM::Bcc; case ARMII::BX_RET: return ARM::BX_RET; - case ARMII::LDRrr: return ARM::LDR; case ARMII::LDRri: return 0; case ARMII::MOVr: return ARM::MOVr; - case ARMII::STRrr: return ARM::STR; case ARMII::STRri: return 0; case ARMII::SUBri: return ARM::SUBri; case ARMII::SUBrs: return ARM::SUBrs; diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp index 19af487..ff98447 100644 --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -38,10 +38,8 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::B: return ARM::tB; case ARMII::Bcc: return ARM::tBcc; case ARMII::BX_RET: return ARM::tBX_RET; - case ARMII::LDRrr: return ARM::tLDR; case ARMII::LDRri: return 0; case ARMII::MOVr: return ARM::tMOVr; - case ARMII::STRrr: return ARM::tSTR; case ARMII::STRri: return 0; case ARMII::SUBri: return ARM::tSUBi8; case ARMII::SUBrs: return 0; diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 421f7f9..53b6007 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -39,10 +39,8 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::B: return ARM::t2B; case ARMII::Bcc: return ARM::t2Bcc; case ARMII::BX_RET: return ARM::tBX_RET; - case ARMII::LDRrr: return ARM::t2LDRs; case ARMII::LDRri: return ARM::t2LDRi12; case ARMII::MOVr: return ARM::t2MOVr; - case ARMII::STRrr: return ARM::t2STRs; case ARMII::STRri: return ARM::t2STRi12; case ARMII::SUBri: return ARM::t2SUBri; case ARMII::SUBrs: return ARM::t2SUBrs; @@ -102,3 +100,36 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, // Handle SPR, DPR, and QPR copies. return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC); } + +void Thumb2InstrInfo:: +storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + + if (RC == ARM::GPRRegisterClass) { + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI).addImm(0)); + return; + } + + ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC); +} + +void Thumb2InstrInfo:: +loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, int FI, + const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + + if (RC == ARM::GPRRegisterClass) { + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) + .addFrameIndex(FI).addImm(0)); + return; + } + + ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC); +} diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h index ac31707..44c3d82 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h @@ -43,6 +43,16 @@ public: const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const; + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const; + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method).