From: Marek Olšák Date: Wed, 6 May 2020 18:51:50 +0000 (-0400) Subject: radeonsi: disable the L2 cache for CPU read mappings of buffers X-Git-Tag: upstream/21.0.0~9888 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c45a2145f5eaae53d48e3aa7e0f10f2c70f267b0;p=platform%2Fupstream%2Fmesa.git radeonsi: disable the L2 cache for CPU read mappings of buffers for faster copying over PCIe and no need to flush L2 Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index a1805dd..e64b51d 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -479,8 +479,9 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour struct si_resource *staging; assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_TRANSFER_THREAD_SAFE))); - staging = si_resource(pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_STAGING, - box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT))); + staging = si_aligned_buffer_create(ctx->screen, SI_RESOURCE_FLAG_UNCACHED, + PIPE_USAGE_STAGING, + box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256); if (staging) { /* Copy the VRAM buffer to the staging buffer. */ si_sdma_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT,