From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Tue, 22 Apr 2008 21:57:57 +0000 (+0000)
Subject: Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
X-Git-Tag: TizenStudio_2.0_p2.3~11983
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c3bec939efffe46e245268fdfe6a8e1888362a3e;p=sdk%2Femulator%2Fqemu.git

Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
long. Thanks to Paul Brook for noticing that.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4242 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index d5dc96b..106720a 100644
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -800,7 +800,8 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 
 #else
 
-#define PHYS_ADDR_MASK (~0xfff)
+/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
+#define PHYS_ADDR_MASK 0xffffffffff000L
 
 /* return value:
    -1 = cannot handle fault