From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 28 Feb 2018 22:57:23 +0000 (+0000)
Subject: [X86] Regenerate cmpxchg tests
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c38756a992fee4be5cf1a394e1bd24457bb6b3d5;p=platform%2Fupstream%2Fllvm.git

[X86] Regenerate cmpxchg tests

Add 64-bit cmpxchg8b tests

llvm-svn: 326380
---

diff --git a/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll b/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
index 1510b2a..54076ab 100644
--- a/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
+++ b/llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
@@ -1,11 +1,20 @@
-; RUN: llc -mcpu=core-avx2 -mtriple=x86_64 -o - %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
 
 define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
 ; CHECK-LABEL: try_cmpxchg:
-; CHECK: cmpxchg16b
-; CHECK-NOT: cmp
-; CHECK: sete %al
-; CHECK: retq
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq %rcx, %r9
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %r8, %rcx
+; CHECK-NEXT:    movq %r9, %rbx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
   %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   %success = extractvalue { i128, i1 } %pair, 1
   ret i1 %success
@@ -13,10 +22,24 @@ define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
 
 define void @cmpxchg_flow(i128* %addr, i128 %desired, i128 %new) {
 ; CHECK-LABEL: cmpxchg_flow:
-; CHECK: cmpxchg16b
-; CHECK-NOT: cmp
-; CHECK-NOT: set
-; CHECK: {{jne|jeq}}
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq %rcx, %r9
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %r8, %rcx
+; CHECK-NEXT:    movq %r9, %rbx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    jne .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %true
+; CHECK-NEXT:    callq foo
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB1_2: # %false
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
   %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   %success = extractvalue { i128, i1 } %pair, 1
   br i1 %success, label %true, label %false
@@ -33,9 +56,21 @@ false:
 ; Can't use the flags here because cmpxchg16b only sets ZF.
 define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
 ; CHECK-LABEL: cmpxchg_arithcmp:
-; CHECK: cmpxchg16b
-; CHECK: cmpq
-; CHECK: retq
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq %rcx, %r9
+; CHECK-NEXT:    movq %rdx, %r10
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %r8, %rcx
+; CHECK-NEXT:    movq %r9, %rbx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    cmpq %rsi, %rax
+; CHECK-NEXT:    sbbq %r10, %rdx
+; CHECK-NEXT:    setge %al
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
   %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   %oldval = extractvalue { i128, i1 } %pair, 0
   %success = icmp sge i128 %oldval, %desired
@@ -44,10 +79,21 @@ define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
 
 define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
 ; CHECK-LABEL: cmpxchg_zext:
-; CHECK: xorl
-; CHECK: cmpxchg16b
-; CHECK-NOT: cmpq
-; CHECK: sete
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq %rcx, %r9
+; CHECK-NEXT:    xorl %r10d, %r10d
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %r8, %rcx
+; CHECK-NEXT:    movq %r9, %rbx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    sete %r10b
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    movq %r10, %rax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
   %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   %success = extractvalue { i128, i1 } %pair, 1
   %mask = zext i1 %success to i128
@@ -57,10 +103,32 @@ define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
 
 define i128 @cmpxchg_use_eflags_and_val(i128* %addr, i128 %offset) {
 ; CHECK-LABEL: cmpxchg_use_eflags_and_val:
-
-; CHECK: cmpxchg16b
-; CHECK-NOT: cmpq
-; CHECK: jne
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq %rdx, %r8
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %ebx, %ebx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB4_1: # %loop
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movq %rdx, %r9
+; CHECK-NEXT:    movq %rax, %r10
+; CHECK-NEXT:    movq %rax, %rbx
+; CHECK-NEXT:    addq %rsi, %rbx
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    adcq %r8, %rcx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    jne .LBB4_1
+; CHECK-NEXT:  # %bb.2: # %done
+; CHECK-NEXT:    movq %r10, %rax
+; CHECK-NEXT:    movq %r9, %rdx
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
 entry:
   %init = load atomic i128, i128* %addr seq_cst, align 16
   br label %loop
diff --git a/llvm/test/CodeGen/X86/cmpxchg16b.ll b/llvm/test/CodeGen/X86/cmpxchg16b.ll
index f070a46..aa29cc5 100644
--- a/llvm/test/CodeGen/X86/cmpxchg16b.ll
+++ b/llvm/test/CodeGen/X86/cmpxchg16b.ll
@@ -1,10 +1,19 @@
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
 
 ; Basic 128-bit cmpxchg
 define void @t1(i128* nocapture %p) nounwind ssp {
+; CHECK-LABEL: t1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    movl $1, %ebx
+; CHECK-NEXT:    lock cmpxchg16b (%rdi)
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
 entry:
-; CHECK: movl	$1, %ebx
-; CHECK: lock cmpxchg16b
   %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/cmpxchg8b.ll b/llvm/test/CodeGen/X86/cmpxchg8b.ll
new file mode 100644
index 0000000..fa8fff8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/cmpxchg8b.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
+
+; Basic 64-bit cmpxchg
+define void @t1(i64* nocapture %p) nounwind ssp {
+; X86-LABEL: t1:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    pushl %ebx
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    xorl %eax, %eax
+; X86-NEXT:    xorl %edx, %edx
+; X86-NEXT:    xorl %ecx, %ecx
+; X86-NEXT:    movl $1, %ebx
+; X86-NEXT:    lock cmpxchg8b (%esi)
+; X86-NEXT:    popl %esi
+; X86-NEXT:    popl %ebx
+; X86-NEXT:    retl
+;
+; X64-LABEL: t1:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl $1, %ecx
+; X64-NEXT:    xorl %eax, %eax
+; X64-NEXT:    lock cmpxchgq %rcx, (%rdi)
+; X64-NEXT:    retq
+entry:
+  %r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
+  ret void
+}
+