From: Jordan Justen <jordan.l.justen@intel.com>
Date: Mon, 25 May 2020 09:51:36 +0000 (-0700)
Subject: anv: Use correct CCS0 aux-map register offset in pipe flush
X-Git-Tag: upstream/23.3.3~5877
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c328638b3b2e156ca53c904bff0c15b1a649c54f;p=platform%2Fupstream%2Fmesa.git

anv: Use correct CCS0 aux-map register offset in pipe flush

According to Bspec, COMPCS0_CCS_AUX_INV register offset
is 042C8h and COMPCS0_AUX_TABLE_BASE_ADDR is defined to 042C0h.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958>
---

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index c4ef46f..d7a129a 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1672,7 +1672,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
 #if GFX_VER == 12
       if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info->has_aux_map) {
          uint64_t register_addr =
-            current_pipeline == GPGPU ? GENX(CCS_CCS_AUX_INV_num) :
+            current_pipeline == GPGPU ? GENX(COMPCS0_CCS_AUX_INV_num) :
                                         GENX(GFX_CCS_AUX_INV_num);
          anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
             lri.RegisterOffset = register_addr;
@@ -1692,6 +1692,8 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
                anv_address_from_u64(register_addr);
          }
       }
+#else
+      assert(!device->info->has_aux_map);
 #endif
 
       bits &= ~ANV_PIPE_INVALIDATE_BITS;