From: Emil Renner Berthing <kernel@esmil.dk>
Date: Tue, 5 Apr 2022 23:04:45 +0000 (+0200)
Subject: dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c31b2af9d111e1f25edd1684eda9f957b1b5cd71;p=platform%2Fkernel%2Flinux-starfive.git

dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs

This cache controller is also used on the StarFive JH7100 and JH7110
SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---

diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..41eb60da04a4 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -25,6 +25,8 @@ select:
           - sifive,ccache0
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7100-ccache
+          - starfive,jh7110-ccache
 
   required:
     - compatible
@@ -37,6 +39,8 @@ properties:
               - sifive,ccache0
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
+              - starfive,jh7110-ccache
           - const: cache
       - items:
           - const: microchip,mpfs-ccache