From: Vinay Kumar Date: Tue, 27 Oct 2015 15:24:40 +0000 (+0000) Subject: Fix RL78 disassembly of DE+offset addressing to always show the offset, even when... X-Git-Tag: users/ARM/embedded-binutils-2_26-branch-2016q1~278 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c2f2875869a3e427435ea04bcd416ee2f99e7ee9;p=external%2Fbinutils.git Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero. PR binutils/19159 opcodes * rl78-decode.opc (MOV): Added offset to DE register in index addressing mode. * rl78-decode.c: Regenerate. test * gas/rl78/pr19159.s: New test source file. * gas/rl78/pr19159.d: New test case. * gas/rl78/rl78.exp: Run the new test. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 08303ee..02b82df 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,12 @@ 2015-10-27 Nick Clifton + PR binutils/19159 + * gas/rl78/pr19159.s: New test source file. + * gas/rl78/pr19159.d: New test case. + * gas/rl78/rl78.exp: Run the new test. + +2015-10-27 Nick Clifton + PR binutils/19158 * gas/rl78/pr19158.s: New test source file. * gas/rl78/pr19158.d: New test case. diff --git a/gas/testsuite/gas/rl78/pr19157.d b/gas/testsuite/gas/rl78/pr19157.d index 9bbbc10..5416457 100644 --- a/gas/testsuite/gas/rl78/pr19157.d +++ b/gas/testsuite/gas/rl78/pr19157.d @@ -1,5 +1,5 @@ #objdump: -d --prefix-addresses --show-raw-insn -#name: PR19157: RL78: zero offset omitted +#name: PR19157: RL78: zero offset omitted in stack based addressing .*: +file format .*rl78.* diff --git a/gas/testsuite/gas/rl78/pr19159.d b/gas/testsuite/gas/rl78/pr19159.d new file mode 100644 index 0000000..f9bfd24 --- /dev/null +++ b/gas/testsuite/gas/rl78/pr19159.d @@ -0,0 +1,15 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: PR19159: RL78: zero offset omitted in DE based addressing + +.*: +file format .*rl78.* + +Disassembly of section .text: +0x0+000 89[ ]+mov[ ]+a, \[de\] +0x0+001 8a 00[ ]+mov[ ]+a, \[de\+0\] +0x0+003 8a 01[ ]+mov[ ]+a, \[de\+1\] +0x0+005 99[ ]+mov[ ]+\[de], a +0x0+006 9a 00[ ]+mov[ ]+\[de\+0\], a +0x0+008 9a 01[ ]+mov[ ]+\[de\+1\], a +0x0+00a a9[ ]+movw[ ]+ax, \[de\] +0x0+00b aa 00[ ]+movw[ ]+ax, \[de\+0\] +0x0+00d aa 01[ ]+movw[ ]+ax, \[de\+1\] diff --git a/gas/testsuite/gas/rl78/pr19159.s b/gas/testsuite/gas/rl78/pr19159.s new file mode 100644 index 0000000..b4be196 --- /dev/null +++ b/gas/testsuite/gas/rl78/pr19159.s @@ -0,0 +1,13 @@ + .text + + mov a, [de] + mov a, [de + 0] + mov a, [de + 1] + mov [de], a + mov [de + 0], a + mov [de + 1], a + movw ax, [de] + movw ax, [de + 0] + movw ax, [de + 1] + + .end diff --git a/gas/testsuite/gas/rl78/rl78.exp b/gas/testsuite/gas/rl78/rl78.exp index 2ec0209..e3d2c40 100644 --- a/gas/testsuite/gas/rl78/rl78.exp +++ b/gas/testsuite/gas/rl78/rl78.exp @@ -21,4 +21,5 @@ if [expr [istarget "rl78-*-*"]] then { run_dump_test "pr19157" run_dump_test "pr19158" + run_dump_test "pr19159" } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dc285c1..d0f7771 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2015-10-27 Vinay + + PR binutils/19159 + * rl78-decode.opc (MOV): Added offset to DE register in index + addressing mode. + * rl78-decode.c: Regenerate. + 2015-10-27 Vinay Kumar PR binutils/19158 diff --git a/opcodes/rl78-decode.c b/opcodes/rl78-decode.c index 902e5fb..fd1fd77 100644 --- a/opcodes/rl78-decode.c +++ b/opcodes/rl78-decode.c @@ -2537,14 +2537,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xaf: { - /** 0110 0001 1010 1111 xch %0, %e1 */ + /** 0110 0001 1010 1111 xch %0, %ea1 */ if (trace) { printf ("\033[33m%s\033[0m %02x %02x\n", - "/** 0110 0001 1010 1111 xch %0, %e1 */", + "/** 0110 0001 1010 1111 xch %0, %ea1 */", op[0], op[1]); } - SYNTAX("xch %0, %e1"); + SYNTAX("xch %0, %ea1"); #line 1210 "rl78-decode.opc" ID(xch); DR(A); SM(DE, IMMU(1)); @@ -4361,14 +4361,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0x8a: { - /** 1000 1010 mov %0, %e1 */ + /** 1000 1010 mov %0, %ea1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1000 1010 mov %0, %e1 */", + "/** 1000 1010 mov %0, %ea1 */", op[0]); } - SYNTAX("mov %0, %e1"); + SYNTAX("mov %0, %ea1"); #line 651 "rl78-decode.opc" ID(mov); DR(A); SM(DE, IMMU(1)); @@ -4506,14 +4506,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0x9a: { - /** 1001 1010 mov %e0, %1 */ + /** 1001 1010 mov %ea0, %1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1001 1010 mov %e0, %1 */", + "/** 1001 1010 mov %ea0, %1 */", op[0]); } - SYNTAX("mov %e0, %1"); + SYNTAX("mov %ea0, %1"); #line 621 "rl78-decode.opc" ID(mov); DM(DE, IMMU(1)); SR(A); @@ -4713,14 +4713,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xaa: { - /** 1010 1010 movw %0, %e1 */ + /** 1010 1010 movw %0, %ea1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1010 1010 movw %0, %e1 */", + "/** 1010 1010 movw %0, %ea1 */", op[0]); } - SYNTAX("movw %0, %e1"); + SYNTAX("movw %0, %ea1"); #line 841 "rl78-decode.opc" ID(mov); W(); DR(AX); SM(DE, IMMU(1)); @@ -4919,14 +4919,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xba: { - /** 1011 1010 movw %e0, %1 */ + /** 1011 1010 movw %ea0, %1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1011 1010 movw %e0, %1 */", + "/** 1011 1010 movw %ea0, %1 */", op[0]); } - SYNTAX("movw %e0, %1"); + SYNTAX("movw %ea0, %1"); #line 822 "rl78-decode.opc" ID(mov); W(); DM(DE, IMMU(1)); SR(AX); @@ -5083,14 +5083,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xca: { - /** 1100 1010 mov %e0, #%1 */ + /** 1100 1010 mov %ea0, #%1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1100 1010 mov %e0, #%1 */", + "/** 1100 1010 mov %ea0, #%1 */", op[0]); } - SYNTAX("mov %e0, #%1"); + SYNTAX("mov %ea0, #%1"); #line 618 "rl78-decode.opc" ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc index 28362c1..6e84959 100644 --- a/opcodes/rl78-decode.opc +++ b/opcodes/rl78-decode.opc @@ -614,10 +614,10 @@ rl78_decode_opcode (unsigned long pc AU, /** 1001 1001 mov %e0, %1 */ ID(mov); DM(DE, 0); SR(A); -/** 1100 1010 mov %e0, #%1 */ +/** 1100 1010 mov %ea0, #%1 */ ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); -/** 1001 1010 mov %e0, %1 */ +/** 1001 1010 mov %ea0, %1 */ ID(mov); DM(DE, IMMU(1)); SR(A); /** 1001 1011 mov %e0, %1 */ @@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1000 1001 mov %0, %e1 */ ID(mov); DR(A); SM(DE, 0); -/** 1000 1010 mov %0, %e1 */ +/** 1000 1010 mov %0, %ea1 */ ID(mov); DR(A); SM(DE, IMMU(1)); /** 1000 1011 mov %0, %e1 */ @@ -818,7 +818,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1011 1001 movw %e0, %1 */ ID(mov); W(); DM(DE, 0); SR(AX); -/** 1011 1010 movw %e0, %1 */ +/** 1011 1010 movw %ea0, %1 */ ID(mov); W(); DM(DE, IMMU(1)); SR(AX); /** 1011 1011 movw %e0, %1 */ @@ -837,7 +837,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1010 1001 movw %0, %e1 */ ID(mov); W(); DR(AX); SM(DE, 0); -/** 1010 1010 movw %0, %e1 */ +/** 1010 1010 movw %0, %ea1 */ ID(mov); W(); DR(AX); SM(DE, IMMU(1)); /** 1010 1011 movw %0, %e1 */ @@ -1206,7 +1206,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1010 1110 xch %0, %e1 */ ID(xch); DR(A); SM(DE, 0); -/** 0110 0001 1010 1111 xch %0, %e1 */ +/** 0110 0001 1010 1111 xch %0, %ea1 */ ID(xch); DR(A); SM(DE, IMMU(1)); /** 0110 0001 1010 1100 xch %0, %e1 */