From: Tilmann Scheller <t.scheller@samsung.com>
Date: Wed, 23 Jul 2014 08:12:51 +0000 (+0000)
Subject: [ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c28f0d587d07c4d78d7e90b9bf16aa4ca9da5447;p=platform%2Fupstream%2Fllvm.git

[ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions.

The post-indexed instructions were missing the constraint, causing unpredictable STRH instructions to be emitted.

The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed.

llvm-svn: 213729
---

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index f0e145a..70c779d 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2830,7 +2830,8 @@ def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
 def STRH_PRE  : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
                            (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
                            StMiscFrm, IIC_iStore_bh_ru,
-                           "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
+                           "strh", "\t$Rt, $addr!",
+                           "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
   bits<14> addr;
   let Inst{23}    = addr{8};      // U bit
   let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
@@ -2843,7 +2844,8 @@ def STRH_PRE  : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
                        (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
                        IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
-                       "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
+                       "strh", "\t$Rt, $addr, $offset",
+                       "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
                    [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
                                                       addr_offset_none:$addr,
                                                       am3offset:$offset))]> {
diff --git a/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll b/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
index 9ea762a..b65dc0c 100644
--- a/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
+++ b/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
@@ -4,10 +4,20 @@
 ; e.g. str r0, [r0], #4
 
 define i32* @earlyclobber-str-post(i32* %addr) nounwind {
-; CHECK: earlyclobber-str-post
+; CHECK-LABEL: earlyclobber-str-post
 ; CHECK-NOT: str r[[REG:[0-9]+]], [r[[REG]]], #4
   %val = ptrtoint i32* %addr to i32
   store i32 %val, i32* %addr
   %new = getelementptr i32* %addr, i32 1
   ret i32* %new
 }
+
+define i16* @earlyclobber-strh-post(i16* %addr) nounwind {
+; CHECK-LABEL: earlyclobber-strh-post
+; CHECK-NOT: strh r[[REG:[0-9]+]], [r[[REG]]], #2
+  %val = ptrtoint i16* %addr to i32
+  %tr = trunc i32 %val to i16
+  store i16 %tr, i16* %addr
+  %new = getelementptr i16* %addr, i32 1
+  ret i16* %new
+}