From: Doug Evans <dje@google.com>
Date: Mon, 3 Aug 1998 19:56:43 +0000 (+0000)
Subject: 	Move all global state data into opcode table struct, and treat
X-Git-Tag: gdb-4_18~1382
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c2009f4a31b33b3615f0425bfac096b9f3055d22;p=external%2Fbinutils.git

	Move all global state data into opcode table struct, and treat
	opcode table as something that is "opened/closed".
	* cgen-asm.c (all fns): New first arg of opcode table descriptor.
	(cgen_asm_init): Delete.
	(cgen_set_parse_operand_fn): New function.
	* cgen-dis.c (all fns): New first arg of opcode table descriptor.
	(cgen_dis_init): Delete.
	* cgen-opc.c (all fns): New first arg of opcode table descriptor.
	(cgen_current_{opcode_table_mach,endian}): Delete.
	* cgen-asm.in (all fns): New first arg of opcode table descriptor.
	* cgen-dis.in (all fns): Ditto.
	* cgen-opc.in (all fns): Ditto.
	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.

	* cgen-asm.in (parse_insn_normal): Ignore case in mnemonics.

	* cgen-dis.in (print_normal): Split into two.
	(print_address): New function.
	(extract_insn_normal): Clarify insn_value arg.
	(print_int_insn): Renamed from print_insn.
	(print_insn): New arg.
	(print_insn_@arch@): Open opcode table if not already done so.
	Move reading of insn into print_insn.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a9bb9c2..a1ba0d3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,33 @@
+Mon Aug  3 12:43:16 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	Move all global state data into opcode table struct, and treat
+	opcode table as something that is "opened/closed".
+	* cgen-asm.c (all fns): New first arg of opcode table descriptor.
+	(cgen_asm_init): Delete.
+	(cgen_set_parse_operand_fn): New function.
+	* cgen-dis.c (all fns): New first arg of opcode table descriptor.
+	(cgen_dis_init): Delete.
+	* cgen-opc.c (all fns): New first arg of opcode table descriptor.
+	(cgen_current_{opcode_table_mach,endian}): Delete.
+start-sanitize-cygnus
+	* cgen-asm.in (all fns): New first arg of opcode table descriptor.
+	* cgen-dis.in (all fns): Ditto.
+	* cgen-opc.in (all fns): Ditto.
+end-sanitize-cygnus
+	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
+
+start-sanitize-cygnus
+	* cgen-asm.in (parse_insn_normal): Ignore case in mnemonics.
+
+	* cgen-dis.in (print_normal): Split into two.
+	(print_address): New function.
+	(extract_insn_normal): Clarify insn_value arg.
+	(print_int_insn): Renamed from print_insn.
+	(print_insn): New arg.
+	(print_insn_@arch@): Open opcode table if not already done so.
+	Move reading of insn into print_insn.
+
+end-sanitize-cygnus
 Thu Jul 30 21:41:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 
 	* d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some
diff --git a/opcodes/cgen-opc.in b/opcodes/cgen-opc.in
index 57a03dd..197daed 100644
--- a/opcodes/cgen-opc.in
+++ b/opcodes/cgen-opc.in
@@ -30,6 +30,14 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "@prefix@-opc.h"
 #include "opintl.h"
 
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
+
 /* Look up instruction INSN_VALUE and extract its fields.
    INSN, if non-null, is the insn table entry.
    Otherwise INSN_VALUE is examined to compute it.
@@ -42,7 +50,8 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
    wasn't recognized.  */
 
 const CGEN_INSN *
-@arch@_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
+@arch@_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN *insn;
      cgen_insn_t insn_value;
      int length;
@@ -62,13 +71,13 @@ const CGEN_INSN *
 	  buf[0] = insn_value;
 	  break;
 	case 16:
-	  if (cgen_current_endian == CGEN_ENDIAN_BIG)
+	  if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
 	    bfd_putb16 (insn_value, buf);
 	  else
 	    bfd_putl16 (insn_value, buf);
 	  break;
 	case 32:
-	  if (cgen_current_endian == CGEN_ENDIAN_BIG)
+	  if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
 	    bfd_putb32 (insn_value, buf);
 	  else
 	    bfd_putl32 (insn_value, buf);
@@ -83,7 +92,7 @@ const CGEN_INSN *
       /* The instructions are stored in hash lists.
 	 Pick the first one and keep trying until we find the right one.  */
 
-      insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
+      insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
       while (insn_list != NULL)
 	{
 	  insn = insn_list->insn;
@@ -97,7 +106,7 @@ const CGEN_INSN *
 	      if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 		{
 		  /* ??? 0 is passed for `pc' */
-		  int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
+		  int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL,
 							   insn_value, fields,
 							   (bfd_vma) 0);
 		  if (elength > 0)
@@ -124,7 +133,7 @@ const CGEN_INSN *
 	abort ();
 
       /* ??? 0 is passed for `pc' */
-      length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
+      length = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL, insn_value, fields,
 					  (bfd_vma) 0);
       /* Sanity check: must succeed.
 	 Could relax this later if it ever proves useful.  */
@@ -141,7 +150,8 @@ const CGEN_INSN *
    in.  */
 
 void
-@arch@_cgen_get_insn_operands (insn, fields, indices)
+@arch@_cgen_get_insn_operands (od, insn, fields, indices)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN * insn;
      const CGEN_FIELDS * fields;
      int *indices;
@@ -172,7 +182,8 @@ void
    recognized.  */
 
 const CGEN_INSN *
-@arch@_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
+@arch@_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN *insn;
      cgen_insn_t insn_value;
      int length;
@@ -182,11 +193,11 @@ const CGEN_INSN *
 
   /* Pass non-zero for ALIAS_P only if INSN != NULL.
      If INSN == NULL, we want a real insn.  */
-  insn = @arch@_cgen_lookup_insn (insn, insn_value, length, &fields,
+  insn = @arch@_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 				  insn != NULL);
   if (! insn)
     return NULL;
 
-  @arch@_cgen_get_insn_operands (insn, &fields, indices);
+  @arch@_cgen_get_insn_operands (od, insn, &fields, indices);
   return insn;
 }
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index a1a1f65..55b8e32 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -30,6 +30,14 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "m32r-opc.h"
 #include "opintl.h"
 
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
+
 /* Look up instruction INSN_VALUE and extract its fields.
    INSN, if non-null, is the insn table entry.
    Otherwise INSN_VALUE is examined to compute it.
@@ -42,7 +50,8 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
    wasn't recognized.  */
 
 const CGEN_INSN *
-m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
+m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN *insn;
      cgen_insn_t insn_value;
      int length;
@@ -62,13 +71,13 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
 	  buf[0] = insn_value;
 	  break;
 	case 16:
-	  if (cgen_current_endian == CGEN_ENDIAN_BIG)
+	  if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
 	    bfd_putb16 (insn_value, buf);
 	  else
 	    bfd_putl16 (insn_value, buf);
 	  break;
 	case 32:
-	  if (cgen_current_endian == CGEN_ENDIAN_BIG)
+	  if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
 	    bfd_putb32 (insn_value, buf);
 	  else
 	    bfd_putl32 (insn_value, buf);
@@ -83,7 +92,7 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
       /* The instructions are stored in hash lists.
 	 Pick the first one and keep trying until we find the right one.  */
 
-      insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
+      insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
       while (insn_list != NULL)
 	{
 	  insn = insn_list->insn;
@@ -97,7 +106,7 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
 	      if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 		{
 		  /* ??? 0 is passed for `pc' */
-		  int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
+		  int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL,
 							   insn_value, fields,
 							   (bfd_vma) 0);
 		  if (elength > 0)
@@ -124,7 +133,7 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
 	abort ();
 
       /* ??? 0 is passed for `pc' */
-      length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
+      length = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL, insn_value, fields,
 					  (bfd_vma) 0);
       /* Sanity check: must succeed.
 	 Could relax this later if it ever proves useful.  */
@@ -141,7 +150,8 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
    in.  */
 
 void
-m32r_cgen_get_insn_operands (insn, fields, indices)
+m32r_cgen_get_insn_operands (od, insn, fields, indices)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN * insn;
      const CGEN_FIELDS * fields;
      int *indices;
@@ -172,7 +182,8 @@ m32r_cgen_get_insn_operands (insn, fields, indices)
    recognized.  */
 
 const CGEN_INSN *
-m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
+m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
+     CGEN_OPCODE_DESC od;
      const CGEN_INSN *insn;
      cgen_insn_t insn_value;
      int length;
@@ -182,12 +193,12 @@ m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
 
   /* Pass non-zero for ALIAS_P only if INSN != NULL.
      If INSN == NULL, we want a real insn.  */
-  insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
+  insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 				  insn != NULL);
   if (! insn)
     return NULL;
 
-  m32r_cgen_get_insn_operands (insn, &fields, indices);
+  m32r_cgen_get_insn_operands (od, insn, &fields, indices);
   return insn;
 }
 /* Attributes.  */
@@ -997,6 +1008,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADD, "add", "add",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xa0,
+    "(set dr (add dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1006,6 +1018,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADD3, "add3", "add3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80a00000,
+    "(set dr (add sr slo16))",
     (PTR) & fmt_add3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1015,6 +1028,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_AND, "and", "and",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xc0,
+    "(set dr (and dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1024,6 +1038,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_AND3, "and3", "and3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80c00000,
+    "(set dr (and sr uimm16))",
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1033,6 +1048,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_OR, "or", "or",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xe0,
+    "(set dr (or dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1042,6 +1058,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_OR3, "or3", "or3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80e00000,
+    "(set dr (or sr ulo16))",
     (PTR) & fmt_or3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1051,6 +1068,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_XOR, "xor", "xor",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xd0,
+    "(set dr (xor dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1060,6 +1078,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_XOR3, "xor3", "xor3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80d00000,
+    "(set dr (xor sr uimm16))",
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1069,6 +1088,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADDI, "addi", "addi",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x4000,
+    "(set dr (add dr simm8))",
     (PTR) & fmt_addi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1078,6 +1098,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADDV, "addv", "addv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x80,
+    "(parallel () (set dr (add dr sr)) (set condbit (add-oflag dr sr (const 0))))",
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1087,6 +1108,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADDV3, "addv3", "addv3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80800000,
+    "(parallel () (set dr (add sr simm16)) (set condbit (add-oflag sr simm16 (const 0))))",
     (PTR) & fmt_addv3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1096,6 +1118,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ADDX, "addx", "addx",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x90,
+    "(parallel () (set dr (addc dr sr condbit)) (set condbit (add-cflag dr sr condbit)))",
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1105,6 +1128,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BC8, "bc8", "bc.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7c00,
+    "(if condbit (set pc disp8))",
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1114,6 +1138,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BC24, "bc24", "bc.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfc000000,
+    "(if condbit (set pc disp24))",
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1123,6 +1148,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BEQ, "beq", "beq",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xf0f00000 }, 0xb0000000,
+    "(if (eq src1 src2) (set pc disp16))",
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1132,6 +1158,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BEQZ, "beqz", "beqz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0800000,
+    "(if (eq src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1141,6 +1168,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BGEZ, "bgez", "bgez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0b00000,
+    "(if (ge src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1150,6 +1178,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BGTZ, "bgtz", "bgtz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0d00000,
+    "(if (gt src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1159,6 +1188,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BLEZ, "blez", "blez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0c00000,
+    "(if (le src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1168,6 +1198,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BLTZ, "bltz", "bltz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0a00000,
+    "(if (lt src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1177,6 +1208,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNEZ, "bnez", "bnez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0900000,
+    "(if (ne src2 (const: WI 0)) (set pc disp16))",
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1186,6 +1218,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BL8, "bl8", "bl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7e00,
+    "(sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8))",
     (PTR) & fmt_bl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1195,6 +1228,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BL24, "bl24", "bl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfe000000,
+    "(sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))",
     (PTR) & fmt_bl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1205,6 +1239,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BCL8, "bcl8", "bcl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7800,
+    "(if condbit (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1216,6 +1251,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BCL24, "bcl24", "bcl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf8000000,
+    "(if condbit (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -1226,6 +1262,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNC8, "bnc8", "bnc.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7d00,
+    "(if (not condbit) (set pc disp8))",
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1235,6 +1272,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNC24, "bnc24", "bnc.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfd000000,
+    "(if (not condbit) (set pc disp24))",
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1244,6 +1282,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNE, "bne", "bne",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xf0f00000 }, 0xb0100000,
+    "(if (ne src1 src2) (set pc disp16))",
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1253,6 +1292,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BRA8, "bra8", "bra.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7f00,
+    "(set pc disp8)",
     (PTR) & fmt_bra8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1262,6 +1302,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BRA24, "bra24", "bra.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xff000000,
+    "(set pc disp24)",
     (PTR) & fmt_bra24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1272,6 +1313,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNCL8, "bncl8", "bncl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7900,
+    "(if (not condbit) (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1283,6 +1325,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_BNCL24, "bncl24", "bncl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf9000000,
+    "(if (not condbit) (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -1293,6 +1336,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMP, "cmp", "cmp",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x40,
+    "(set condbit (lt src1 src2))",
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1302,6 +1346,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMPI, "cmpi", "cmpi",
     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xfff00000 }, 0x80400000,
+    "(set condbit (lt src2 simm16))",
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1311,6 +1356,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMPU, "cmpu", "cmpu",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50,
+    "(set condbit (ltu src1 src2))",
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1320,6 +1366,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMPUI, "cmpui", "cmpui",
     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xfff00000 }, 0x80500000,
+    "(set condbit (ltu src2 simm16))",
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1330,6 +1377,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x60,
+    "(set condbit (eq src1 src2))",
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
@@ -1341,6 +1389,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_CMPZ, "cmpz", "cmpz",
     { { MNEM, ' ', OP (SRC2), 0 } },
     { 16, 16, 0xfff0 }, 0x70,
+    "(set condbit (eq src2 (const 0)))",
     (PTR) & fmt_cmpz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
@@ -1351,6 +1400,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_DIV, "div", "div",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90000000,
+    "(if (ne sr (const 0)) (set dr (div dr sr)))",
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1360,6 +1410,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_DIVU, "divu", "divu",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90100000,
+    "(if (ne sr (const 0)) (set dr (udiv dr sr)))",
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1369,6 +1420,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_REM, "rem", "rem",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90200000,
+    "(if (ne sr (const 0)) (set dr (mod dr sr)))",
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1378,6 +1430,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_REMU, "remu", "remu",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90300000,
+    "(if (ne sr (const 0)) (set dr (umod dr sr)))",
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1388,6 +1441,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_DIVH, "divh", "divh",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90000010,
+    "(if (ne sr (const 0)) (set dr (div (ext: WI (trunc: HI dr)) sr)))",
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -1399,6 +1453,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_JC, "jc", "jc",
     { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1cc0,
+    "(if condbit (set pc (and sr (const -4))))",
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1410,6 +1465,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_JNC, "jnc", "jnc",
     { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1dc0,
+    "(if (not condbit) (set pc (and sr (const -4))))",
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1420,6 +1476,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_JL, "jl", "jl",
     { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1ec0,
+    "(parallel () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc (and sr (const -4))))",
     (PTR) & fmt_jl_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1429,6 +1486,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_JMP, "jmp", "jmp",
     { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1fc0,
+    "(set pc (and sr (const -4)))",
     (PTR) & fmt_jmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1438,6 +1496,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LD, "ld", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20c0,
+    "(set dr (mem: WI sr))",
     (PTR) & fmt_ld_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1447,6 +1506,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LD_D, "ld-d", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0c00000,
+    "(set dr (mem: WI (add sr slo16)))",
     (PTR) & fmt_ld_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1456,6 +1516,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDB, "ldb", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x2080,
+    "(set dr (ext: WI (mem: QI sr)))",
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1465,6 +1526,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDB_D, "ldb-d", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0800000,
+    "(set dr (ext: WI (mem: QI (add sr slo16))))",
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1474,6 +1536,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDH, "ldh", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20a0,
+    "(set dr (ext: WI (mem: HI sr)))",
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1483,6 +1546,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDH_D, "ldh-d", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0a00000,
+    "(set dr (ext: WI (mem: HI (add sr slo16))))",
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1492,6 +1556,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDUB, "ldub", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x2090,
+    "(set dr (zext: WI (mem: QI sr)))",
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1501,6 +1566,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDUB_D, "ldub-d", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0900000,
+    "(set dr (zext: WI (mem: QI (add sr slo16))))",
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1510,6 +1576,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDUH, "lduh", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20b0,
+    "(set dr (zext: WI (mem: HI sr)))",
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1519,6 +1586,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDUH_D, "lduh-d", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0b00000,
+    "(set dr (zext: WI (mem: HI (add sr slo16))))",
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1528,6 +1596,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LD_PLUS, "ld-plus", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
     { 16, 16, 0xf0f0 }, 0x20e0,
+    "(parallel () (set dr (mem: WI sr)) (set sr (add sr (const 4))))",
     (PTR) & fmt_ld_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1537,6 +1606,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LD24, "ld24", "ld24",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
     { 32, 32, 0xf0000000 }, 0xe0000000,
+    "(set dr uimm24)",
     (PTR) & fmt_ld24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1546,6 +1616,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDI8, "ldi8", "ldi8",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x6000,
+    "(set dr simm8)",
     (PTR) & fmt_ldi8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1555,6 +1626,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LDI16, "ldi16", "ldi16",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0x90f00000,
+    "(set dr slo16)",
     (PTR) & fmt_ldi16_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1564,6 +1636,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_LOCK, "lock", "lock",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20d0,
+    "(sequence () (set (reg h-lock) (const: UBI 1)) (set dr (mem: WI sr)))",
     (PTR) & fmt_lock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1573,6 +1646,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACHI, "machi", "machi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3040,
+    "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1583,6 +1657,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACHI_A, "machi-a", "machi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3040,
+    "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1593,6 +1668,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACLO, "maclo", "maclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3050,
+    "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1603,6 +1679,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACLO_A, "maclo-a", "maclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3050,
+    "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1613,24 +1690,51 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACWHI, "macwhi", "macwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3060,
+    "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
+/* start-sanitize-m32rx */
+/* macwhi $src1,$src2,$acc */
+  {
+    { 1, 1, 1, 1 },
+    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    { 16, 16, 0xf070 }, 0x3060,
+    "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16)))))))",
+    (PTR) & fmt_machi_a_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* end-sanitize-m32rx */
 /* macwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACWLO, "macwlo", "macwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3070,
+    "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
+/* start-sanitize-m32rx */
+/* macwlo $src1,$src2,$acc */
+  {
+    { 1, 1, 1, 1 },
+    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    { 16, 16, 0xf070 }, 0x3070,
+    "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI src2)))))",
+    (PTR) & fmt_machi_a_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* end-sanitize-m32rx */
 /* mul $dr,$sr */
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MUL, "mul", "mul",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1060,
+    "(set dr (mul dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1640,6 +1744,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULHI, "mulhi", "mulhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3000,
+    "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1650,6 +1755,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3000,
+    "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1660,6 +1766,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULLO, "mullo", "mullo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3010,
+    "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1670,6 +1777,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULLO_A, "mullo-a", "mullo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3010,
+    "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1680,24 +1788,51 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3020,
+    "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 8)) (const 8)))",
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
+/* start-sanitize-m32rx */
+/* mulwhi $src1,$src2,$acc */
+  {
+    { 1, 1, 1, 1 },
+    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    { 16, 16, 0xf070 }, 0x3020,
+    "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16))))))",
+    (PTR) & fmt_mulhi_a_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* end-sanitize-m32rx */
 /* mulwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3030,
+    "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2))) (const 8)) (const 8)))",
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
+/* start-sanitize-m32rx */
+/* mulwlo $src1,$src2,$acc */
+  {
+    { 1, 1, 1, 1 },
+    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    { 16, 16, 0xf070 }, 0x3030,
+    "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI src2))))",
+    (PTR) & fmt_mulhi_a_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* end-sanitize-m32rx */
 /* mv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MV, "mv", "mv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1080,
+    "(set dr sr)",
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1707,6 +1842,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
     { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f0,
+    "(set dr (trunc: WI (sra: DI accum (const 32))))",
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1717,6 +1853,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f0,
+    "(set dr (trunc: WI (sra: DI accs (const 32))))",
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1727,6 +1864,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
     { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f1,
+    "(set dr (trunc: WI accum))",
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1737,6 +1875,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f1,
+    "(set dr (trunc: WI accs))",
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1747,6 +1886,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
     { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f2,
+    "(set dr (trunc: WI (sra: DI accum (const 16))))",
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1757,6 +1897,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f2,
+    "(set dr (trunc: WI (sra: DI accs (const 16))))",
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1767,6 +1908,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVFC, "mvfc", "mvfc",
     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1090,
+    "(set dr scr)",
     (PTR) & fmt_mvfc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1776,6 +1918,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
     { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x5070,
+    "(set accum (or: DI (and: DI accum (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1786,6 +1929,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x5070,
+    "(set accs (or: DI (and: DI accs (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1796,6 +1940,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
     { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x5071,
+    "(set accum (or: DI (and: DI accum (const: DI 18446744069414584320)) (zext: DI src1)))",
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1806,6 +1951,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x5071,
+    "(set accs (or: DI (and: DI accs (const: DI 18446744069414584320)) (zext: DI src1)))",
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1816,6 +1962,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MVTC, "mvtc", "mvtc",
     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
     { 16, 16, 0xf0f0 }, 0x10a0,
+    "(set dcr sr)",
     (PTR) & fmt_mvtc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1825,6 +1972,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_NEG, "neg", "neg",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x30,
+    "(set dr (neg sr))",
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1834,6 +1982,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_NOP, "nop", "nop",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7000,
+    "(c-code: VM PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+)",
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1843,6 +1993,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_NOT, "not", "not",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xb0,
+    "(set dr (inv sr))",
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -1852,6 +2003,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_RAC, "rac", "rac",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x5090,
+    "(sequence ((DI tmp1)) (set tmp1 (sll: DI accum (const 1))) (set tmp1 (add: DI tmp1 (const: DI 32768))) (set accum (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1862,6 +2014,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
     { 16, 16, 0xf3f2 }, 0x5090,
+    "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 32768))) (set accd (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1872,6 +2025,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_RACH, "rach", "rach",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x5080,
+    "(sequence ((DI tmp1)) (set tmp1 (and accum (const: DI 72057594037927935))) (if (andif: WI (ge tmp1 (const: DI 70366596694016)) (le tmp1 (const: DI 36028797018963967))) (set tmp1 (const: DI 70366596694016)) (if (andif: WI (ge tmp1 (const: DI 36028797018963968)) (le tmp1 (const: DI 71987225293750272))) (set tmp1 (const: DI 71987225293750272)) (set tmp1 (and (add accum (const: DI 1073741824)) (const: DI 18446744071562067968))))) (set tmp1 (sll tmp1 (const 1))) (set accum (sra: DI (sll: DI tmp1 (const 7)) (const 7))))",
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -1882,6 +2036,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
     { 16, 16, 0xf3f2 }, 0x5080,
+    "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 2147483648))) (set accd (cond: DI ((gt tmp1 (const: DI 140733193388032)) (const: DI 140733193388032)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744069414584320))))))",
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -1892,6 +2047,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_RTE, "rte", "rte",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x10d6,
+    "(sequence () (set (reg h-sm) (reg h-bsm)) (set (reg h-ie) (reg h-bie)) (set condbit (reg h-bcond)) (set pc (and (reg h-bpc) (const -4))))",
     (PTR) & fmt_rte_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1901,6 +2057,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SETH, "seth", "seth",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
+    "(set dr (sll: WI hi16 (const 16)))",
     (PTR) & fmt_seth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1910,6 +2067,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SLL, "sll", "sll",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1040,
+    "(set dr (sll dr (and sr (const 31))))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1919,6 +2077,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SLL3, "sll3", "sll3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90c00000,
+    "(set dr (sll sr (and: WI simm16 (const 31))))",
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1928,6 +2087,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SLLI, "slli", "slli",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5040,
+    "(set dr (sll dr uimm5))",
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1937,6 +2097,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRA, "sra", "sra",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1020,
+    "(set dr (sra dr (and sr (const 31))))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1946,6 +2107,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRA3, "sra3", "sra3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90a00000,
+    "(set dr (sra sr (and: WI simm16 (const 31))))",
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1955,6 +2117,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRAI, "srai", "srai",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5020,
+    "(set dr (sra dr uimm5))",
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1964,6 +2127,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRL, "srl", "srl",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1000,
+    "(set dr (srl dr (and sr (const 31))))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1973,6 +2137,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRL3, "srl3", "srl3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90800000,
+    "(set dr (srl sr (and: WI simm16 (const 31))))",
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -1982,6 +2147,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SRLI, "srli", "srli",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5000,
+    "(set dr (srl dr uimm5))",
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -1991,6 +2157,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ST, "st", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2040,
+    "(set: WI (mem: WI src2) src1)",
     (PTR) & fmt_st_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2000,6 +2167,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ST_D, "st-d", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0400000,
+    "(set: WI (mem: WI (add src2 slo16)) src1)",
     (PTR) & fmt_st_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2009,6 +2177,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_STB, "stb", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2000,
+    "(set: QI (mem: QI src2) src1)",
     (PTR) & fmt_stb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2018,6 +2187,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_STB_D, "stb-d", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0000000,
+    "(set: QI (mem: QI (add src2 slo16)) src1)",
     (PTR) & fmt_stb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2027,6 +2197,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_STH, "sth", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2020,
+    "(set: HI (mem: HI src2) src1)",
     (PTR) & fmt_sth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2036,6 +2207,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_STH_D, "sth-d", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0200000,
+    "(set: HI (mem: HI (add src2 slo16)) src1)",
     (PTR) & fmt_sth_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2045,6 +2217,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ST_PLUS, "st-plus", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2060,
+    "(sequence ((WI new-src2)) (set new-src2 (add: WI src2 (const: WI 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2054,6 +2227,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_ST_MINUS, "st-minus", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2070,
+    "(sequence ((WI new-src2)) (set new-src2 (sub src2 (const 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2063,6 +2237,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SUB, "sub", "sub",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20,
+    "(set dr (sub dr sr))",
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -2072,6 +2247,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SUBV, "subv", "subv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x0,
+    "(parallel () (set dr (sub dr sr)) (set condbit (sub-oflag dr sr (const 0))))",
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -2081,6 +2257,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SUBX, "subx", "subx",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x10,
+    "(parallel () (set dr (subc dr sr condbit)) (set condbit (sub-cflag dr sr condbit)))",
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -2090,6 +2267,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_TRAP, "trap", "trap",
     { { MNEM, ' ', OP (UIMM4), 0 } },
     { 16, 16, 0xfff0 }, 0x10f0,
+    "(sequence () (set (reg h-cr 6) (add pc (const 4))) (set (reg h-cr 0) (and (sll (reg h-cr 0) (const 8)) (const 65408))) (set: WI pc (c-call: WI m32r_trap uimm4)))",
     (PTR) & fmt_trap_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2099,6 +2277,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_UNLOCK, "unlock", "unlock",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2050,
+    "(sequence () (if (reg h-lock) (set (mem: WI src2) src1)) (set (reg h-lock) (const: UBI 0)))",
     (PTR) & fmt_unlock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2109,6 +2288,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SATB, "satb", "satb",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600300,
+    "(set dr (cond: WI ((ge sr (const 127)) (const 127)) ((le sr (const -128)) (const -128)) (else sr)))",
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2120,6 +2300,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SATH, "sath", "sath",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600200,
+    "(set dr (cond: WI ((ge sr (const 32767)) (const 32767)) ((le sr (const -32768)) (const -32768)) (else sr)))",
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2131,6 +2312,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SAT, "sat", "sat",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600000,
+    "(set dr (if: WI condbit (if: WI (lt sr (const 0)) (const 2147483647) (const 2147483648)) sr))",
     (PTR) & fmt_sat_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2142,8 +2324,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
     { { MNEM, ' ', OP (SRC2), 0 } },
     { 16, 16, 0xfff0 }, 0x370,
+    "(set condbit (cond: BI ((eq (and src2 (const 255)) (const 0)) (const: BI 1)) ((eq (and src2 (const 65280)) (const 0)) (const: BI 1)) ((eq (and src2 (const 16711680)) (const 0)) (const: BI 1)) ((eq (and src2 (const 4278190080)) (const 0)) (const: BI 1)) (else (const: BI 0))))",
     (PTR) & fmt_cmpz_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2153,6 +2336,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SADD, "sadd", "sadd",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x50e4,
+    "(set (reg h-accums 0) (add (sra (reg h-accums 1) (const 16)) (reg h-accums 0)))",
     (PTR) & fmt_sadd_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2164,6 +2348,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACWU1, "macwu1", "macwu1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50b0,
+    "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535))))) (const 8)) (const 8)))",
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2175,6 +2360,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MSBLO, "msblo", "msblo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50d0,
+    "(set accum (sra: DI (sll: DI (sub accum (sra: DI (sll: DI (mul: DI (ext: DI (trunc: HI src1)) (ext: DI (trunc: HI src2))) (const 32)) (const 16))) (const 8)) (const 8)))",
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2186,6 +2372,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50a0,
+    "(set (reg h-accums 1) (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535)))) (const 16)) (const 16)))",
     (PTR) & fmt_mulwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2197,6 +2384,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_MACLH1, "maclh1", "maclh1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50c0,
+    "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (sll: DI (ext: DI (mul: SI (ext: SI (trunc: HI src1)) (sra: SI src2 (const: SI 16)))) (const 16))) (const 8)) (const 8)))",
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2208,6 +2396,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SC, "sc", "sc",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7401,
+    "(if condbit (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
+))",
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2219,6 +2409,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     M32R_INSN_SNC, "snc", "snc",
     { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7501,
+    "(if (not condbit) (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
+))",
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2229,7 +2421,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 #undef MNEM
 #undef OP
 
-static CGEN_INSN_TABLE insn_table =
+static const CGEN_INSN_TABLE insn_table =
 {
   & m32r_cgen_insn_table_entries[0],
   sizeof (CGEN_INSN),
@@ -2253,6 +2445,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bc8r", "bc",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7c00,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2262,6 +2455,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bc24r", "bc",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfc000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2271,6 +2465,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bl8r", "bl",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7e00,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2280,6 +2475,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bl24r", "bl",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfe000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2289,6 +2485,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bcl8r", "bcl",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7800,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2298,6 +2495,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bcl24r", "bcl",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf8000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2307,6 +2505,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bnc8r", "bnc",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7d00,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2316,6 +2515,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bnc24r", "bnc",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfd000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2325,6 +2525,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bra8r", "bra",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7f00,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2334,6 +2535,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bra24r", "bra",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xff000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2343,6 +2545,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bncl8r", "bncl",
     { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7900,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2352,6 +2555,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "bncl24r", "bncl",
     { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf9000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2361,6 +2565,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ld-2", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20c0,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2370,6 +2575,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ld-d2", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0c00000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2379,6 +2585,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldb-2", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2080,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2388,6 +2595,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldb-d2", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0800000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2397,6 +2605,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldh-2", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20a0,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2406,6 +2615,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldh-d2", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0a00000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2415,6 +2625,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldub-2", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2090,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2424,6 +2635,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldub-d2", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0900000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2433,6 +2645,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "lduh-2", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20b0,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2442,6 +2655,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "lduh-d2", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0b00000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2451,6 +2665,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "pop", "pop",
     { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x20ef,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2460,6 +2675,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldi8a", "ldi",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x6000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
@@ -2469,6 +2685,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "ldi16a", "ldi",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0x90f00000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2478,6 +2695,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "rac-d", "rac",
     { { MNEM, ' ', OP (ACCD), 0 } },
     { 16, 16, 0xf3ff }, 0x5090,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2487,6 +2705,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "rac-ds", "rac",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf3f3 }, 0x5090,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2496,6 +2715,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "rach-d", "rach",
     { { MNEM, ' ', OP (ACCD), 0 } },
     { 16, 16, 0xf3ff }, 0x5080,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2505,6 +2725,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "rach-ds", "rach",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf3f3 }, 0x5080,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2514,6 +2735,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "st-2", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2040,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2523,6 +2745,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "st-d2", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0400000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2532,6 +2755,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "stb-2", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2541,6 +2765,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "stb-d2", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0000000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2550,6 +2775,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "sth-2", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2020,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
@@ -2559,6 +2785,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "sth-d2", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0200000,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2568,6 +2795,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     -1, "push", "push",
     { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x207f,
+    0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
@@ -2577,7 +2805,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
 #undef MNEM
 #undef OP
 
-static CGEN_INSN_TABLE macro_insn_table =
+static const CGEN_INSN_TABLE macro_insn_table =
 {
   & macro_insn_table_entries[0],
   sizeof (CGEN_INSN),
@@ -2586,13 +2814,10 @@ static CGEN_INSN_TABLE macro_insn_table =
   NULL
 };
 
-/* The hash functions are recorded here to help keep assembler code out of
-   the disassembler and vice versa.  */
-
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
+static void
+init_tables ()
+{
+}
 
 /* Return non-zero if INSN is to be added to the hash table.
    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
@@ -2633,20 +2858,54 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
+/* Initialize an opcode table and return a descriptor.
+   It's much like opening a file, and must be the first function called.  */
+
+CGEN_OPCODE_DESC
+m32r_cgen_opcode_open (mach, endian)
+     int mach;
+     enum cgen_endian endian;
 {
-  & m32r_cgen_hw_entries[0],
-  /*& m32r_cgen_operand_table[0], - FIXME:wip */
-  & insn_table,
-  & macro_insn_table,
-  asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
-  dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
-};
+  CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
+  static int init_p;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (table, 0, sizeof (*table));
+
+  CGEN_OPCODE_MACH (table) = mach;
+  CGEN_OPCODE_ENDIAN (table) = endian;
+
+  CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
+
+  CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
+
+  * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
+
+  * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
+
+  CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
+  CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
+  CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
+
+  CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
+  CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
+  CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
+
+  return (CGEN_OPCODE_DESC) table;
+}
+
+/* Close an opcode table.  */
 
 void
-m32r_cgen_init_tables (mach)
-    int mach;
+m32r_cgen_opcode_close (desc)
+     CGEN_OPCODE_DESC desc;
 {
+  free (desc);
 }
 
 /* Getting values from cgen_fields is handled by a collection of functions.
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index bdd7fe7..d87afea 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -226,7 +226,15 @@ typedef enum cgen_insn_type {
 /* start-sanitize-m32rx */
  , M32R_INSN_MACLO_A
 /* end-sanitize-m32rx */
- , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
+ , M32R_INSN_MACWHI
+/* start-sanitize-m32rx */
+ , M32R_INSN_MACWHI_A
+/* end-sanitize-m32rx */
+ , M32R_INSN_MACWLO
+/* start-sanitize-m32rx */
+ , M32R_INSN_MACWLO_A
+/* end-sanitize-m32rx */
+ , M32R_INSN_MUL, M32R_INSN_MULHI
 /* start-sanitize-m32rx */
  , M32R_INSN_MULHI_A
 /* end-sanitize-m32rx */
@@ -234,7 +242,15 @@ typedef enum cgen_insn_type {
 /* start-sanitize-m32rx */
  , M32R_INSN_MULLO_A
 /* end-sanitize-m32rx */
- , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
+ , M32R_INSN_MULWHI
+/* start-sanitize-m32rx */
+ , M32R_INSN_MULWHI_A
+/* end-sanitize-m32rx */
+ , M32R_INSN_MULWLO
+/* start-sanitize-m32rx */
+ , M32R_INSN_MULWLO_A
+/* end-sanitize-m32rx */
+ , M32R_INSN_MV, M32R_INSN_MVFACHI
 /* start-sanitize-m32rx */
  , M32R_INSN_MVFACHI_A
 /* end-sanitize-m32rx */
@@ -387,16 +403,16 @@ extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 /* end-sanitize-m32rx */
 
-#define CGEN_INIT_PARSE() \
+#define CGEN_INIT_PARSE(od) \
 {\
 }
-#define CGEN_INIT_INSERT() \
+#define CGEN_INIT_INSERT(od) \
 {\
 }
-#define CGEN_INIT_EXTRACT() \
+#define CGEN_INIT_EXTRACT(od) \
 {\
 }
-#define CGEN_INIT_PRINT() \
+#define CGEN_INIT_PRINT(od) \
 {\
 }