From: Tien Fong Chee <tien.fong.chee@intel.com>
Date: Tue, 7 May 2019 09:42:27 +0000 (+0800)
Subject: ARM: socfpga: Moving the watchdog reset to the for-loop status polling
X-Git-Tag: v2019.07-rc2~4^2~12
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c1cf5391807640159edcd363ea1cbaf226a56b58;p=platform%2Fkernel%2Fu-boot.git

ARM: socfpga: Moving the watchdog reset to the for-loop status polling

Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index b0abe19..9499d1a 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
 			printf("nstatus == 0 while waiting for condone\n");
 			return -EPERM;
 		}
+		WATCHDOG_RESET();
 	}
 
 	if (i == FPGA_TIMEOUT_CNT)
@@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
 		printf("FPGA: Poll CD failed with error code %d\n", status);
 		return -EPERM;
 	}
-	WATCHDOG_RESET();
 
 	/* Ensure the FPGA entering user mode */
 	status = fpgamgr_program_poll_usermode();