From: Anuj Phogat <anuj.phogat@gmail.com>
Date: Tue, 13 Jun 2017 18:08:48 +0000 (-0700)
Subject: anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}
X-Git-Tag: upstream/18.1.0~8445
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c17e214a6bf1da97c78fa7a6192cb1b498b773a1;p=platform%2Fupstream%2Fmesa.git

anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}

This field is remove from CACHE_MODE_1 register in gen10.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 00c4105..7a16ec0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -55,10 +55,13 @@ genX(init_device_state)(struct anv_device *device)
 #if GEN_GEN >= 9
    uint32_t cache_mode_1;
    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
-                   .PartialResolveDisableInVC = true,
-                   .PartialResolveDisableInVCMask = true,
+#if GEN_GEN == 9
                    .FloatBlendOptimizationEnable = true,
-                   .FloatBlendOptimizationEnableMask = true);
+                   .FloatBlendOptimizationEnableMask = true,
+#endif
+                   .PartialResolveDisableInVC = true,
+                   .PartialResolveDisableInVCMask = true);
+
    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
       lri.RegisterOffset = GENX(CACHE_MODE_1_num);
       lri.DataDWord      = cache_mode_1;