From: Matthias Gehre Date: Mon, 12 Sep 2022 13:27:04 +0000 (+0100) Subject: Move TargetTransformInfo::maxLegalDivRemBitWidth -> TargetLowering::maxSupportedDivRe... X-Git-Tag: upstream/17.0.6~33777 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c1502425ba2d10d75c35e8c00a29aabd8c8e59ba;p=platform%2Fupstream%2Fllvm.git Move TargetTransformInfo::maxLegalDivRemBitWidth -> TargetLowering::maxSupportedDivRemBitWidth Also remove new-pass-manager version of ExpandLargeDivRem because there is no way yet to access TargetLowering in the new pass manager. Differential Revision: https://reviews.llvm.org/D133691 --- diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 2b3c5a0..525b5db 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -687,9 +687,6 @@ public: /// would typically be allowed using throughput or size cost models. bool hasDivRemOp(Type *DataType, bool IsSigned) const; - /// Returns the maximum bitwidth of legal div and rem instructions. - unsigned maxLegalDivRemBitWidth() const; - /// Return true if the given instruction (assumed to be a memory access /// instruction) has a volatile variant. If that's the case then we can avoid /// addrspacecast to generic AS for volatile loads/stores. Default @@ -1644,7 +1641,6 @@ public: const SmallBitVector &OpcodeMask) const = 0; virtual bool enableOrderedReductions() = 0; virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0; - virtual unsigned maxLegalDivRemBitWidth() = 0; virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0; virtual bool prefersVectorizedAddressing() = 0; virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, @@ -2092,9 +2088,6 @@ public: bool hasDivRemOp(Type *DataType, bool IsSigned) override { return Impl.hasDivRemOp(DataType, IsSigned); } - unsigned maxLegalDivRemBitWidth() override { - return Impl.maxLegalDivRemBitWidth(); - } bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override { return Impl.hasVolatileVariant(I, AddrSpace); } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index b744146..8342a82 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -291,10 +291,6 @@ public: bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; } - unsigned maxLegalDivRemBitWidth() const { - return llvm::IntegerType::MAX_INT_BITS; - } - bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const { return false; } diff --git a/llvm/include/llvm/CodeGen/ExpandLargeDivRem.h b/llvm/include/llvm/CodeGen/ExpandLargeDivRem.h deleted file mode 100644 index 15a3421..0000000 --- a/llvm/include/llvm/CodeGen/ExpandLargeDivRem.h +++ /dev/null @@ -1,29 +0,0 @@ -//===----- ExpandLargeDivRem.h - Expand large div/rem ---------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_EXPANDLARGEDIVREM_H -#define LLVM_CODEGEN_EXPANDLARGEDIVREM_H - -#include "llvm/IR/PassManager.h" - -namespace llvm { - -/// Expands div/rem instructions with a bitwidth above a threshold -/// into a loop. -/// This is useful for backends like x86 that cannot lower divisions -/// with more than 128 bits. -class ExpandLargeDivRemPass : public PassInfoMixin { -public: - PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); - - // The backend asserts when seeing large div/rem instructions. - static bool isRequired() { return true; } -}; -} // end namespace llvm - -#endif // LLVM_CODEGEN_EXPANDLARGEDIVREM_H diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 8405fff..fc0fa1c 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -1934,6 +1934,12 @@ public: return MaxAtomicSizeInBitsSupported; } + /// Returns the size in bits of the maximum div/rem the backend supports. + /// Larger operations will be expanded by ExpandLargeDivRem. + unsigned getMaxDivRemBitWidthSupported() const { + return MaxDivRemBitWidthSupported; + } + /// Returns the size of the smallest cmpxchg or ll/sc instruction /// the backend supports. Any smaller operations are widened in /// AtomicExpandPass. @@ -2491,6 +2497,12 @@ protected: MaxAtomicSizeInBitsSupported = SizeInBits; } + /// Set the size in bits of the maximum div/rem the backend supports. + /// Larger operations will be expanded by ExpandLargeDivRem. + void setMaxDivRemBitWidthSupported(unsigned SizeInBits) { + MaxDivRemBitWidthSupported = SizeInBits; + } + /// Sets the minimum cmpxchg or ll/sc size supported by the backend. void setMinCmpXchgSizeInBits(unsigned SizeInBits) { MinCmpXchgSizeInBits = SizeInBits; @@ -3179,6 +3191,10 @@ private: /// Accesses larger than this will be expanded by AtomicExpandPass. unsigned MaxAtomicSizeInBitsSupported; + /// Size in bits of the maximum div/rem size the backend supports. + /// Larger operations will be expanded by ExpandLargeDivRem. + unsigned MaxDivRemBitWidthSupported; + /// Size in bits of the minimum cmpxchg or ll/sc operation the /// backend supports. unsigned MinCmpXchgSizeInBits; @@ -4573,6 +4589,7 @@ public: //===--------------------------------------------------------------------===// // Div utility functions // + SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl &Created) const; SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 46b3966..d009f2f 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -451,10 +451,6 @@ bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const { return TTIImpl->hasDivRemOp(DataType, IsSigned); } -unsigned TargetTransformInfo::maxLegalDivRemBitWidth() const { - return TTIImpl->maxLegalDivRemBitWidth(); -} - bool TargetTransformInfo::hasVolatileVariant(Instruction *I, unsigned AddrSpace) const { return TTIImpl->hasVolatileVariant(I, AddrSpace); diff --git a/llvm/lib/CodeGen/ExpandLargeDivRem.cpp b/llvm/lib/CodeGen/ExpandLargeDivRem.cpp index 1fa2993..f8ffc2b 100644 --- a/llvm/lib/CodeGen/ExpandLargeDivRem.cpp +++ b/llvm/lib/CodeGen/ExpandLargeDivRem.cpp @@ -14,18 +14,20 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Analysis/GlobalsModRef.h" -#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetLowering.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InstIterator.h" #include "llvm/IR/PassManager.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/Utils/IntegerDivision.h" using namespace llvm; @@ -51,11 +53,11 @@ static bool isSigned(unsigned int Opcode) { return Opcode == Instruction::SDiv || Opcode == Instruction::SRem; } -static bool runImpl(Function &F, const TargetTransformInfo &TTI) { +static bool runImpl(Function &F, const TargetLowering &TLI) { SmallVector Replace; bool Modified = false; - unsigned MaxLegalDivRemBitWidth = TTI.maxLegalDivRemBitWidth(); + unsigned MaxLegalDivRemBitWidth = TLI.getMaxDivRemBitWidthSupported(); if (ExpandDivRemBits != llvm::IntegerType::MAX_INT_BITS) MaxLegalDivRemBitWidth = ExpandDivRemBits; @@ -103,17 +105,6 @@ static bool runImpl(Function &F, const TargetTransformInfo &TTI) { return Modified; } -PreservedAnalyses ExpandLargeDivRemPass::run(Function &F, - FunctionAnalysisManager &AM) { - TargetTransformInfo &TTI = AM.getResult(F); - bool Changed = runImpl(F, TTI); - - if (Changed) - return PreservedAnalyses::none(); - - return PreservedAnalyses::all(); -} - class ExpandLargeDivRemLegacyPass : public FunctionPass { public: static char ID; @@ -123,12 +114,13 @@ public: } bool runOnFunction(Function &F) override { - auto &TTI = getAnalysis().getTTI(F); - return runImpl(F, TTI); + auto *TM = &getAnalysis().getTM(); + auto *TLI = TM->getSubtargetImpl(F)->getTargetLowering(); + return runImpl(F, *TLI); } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addPreserved(); AU.addPreserved(); } diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 0994936..8eaf1bb 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -724,6 +724,8 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { // with the Target-specific changes necessary. MaxAtomicSizeInBitsSupported = 1024; + MaxDivRemBitWidthSupported = llvm::IntegerType::MAX_INT_BITS; + MinCmpXchgSizeInBits = 0; SupportsUnalignedAtomics = false; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index e985d34..4a77778 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -955,6 +955,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setHasExtractBitsInsn(true); + setMaxDivRemBitWidthSupported(128); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); if (Subtarget->hasNEON()) { diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 473a00d..eef5295 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -328,8 +328,6 @@ public: bool enableOrderedReductions() const { return true; } - unsigned maxLegalDivRemBitWidth() const { return 128; } - InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 350453d..6ffaec9 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1380,6 +1380,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setMaxAtomicSizeInBitsSupported(0); } + setMaxDivRemBitWidthSupported(64); + setOperationAction(ISD::PREFETCH, MVT::Other, Custom); // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index 3466be0..c018092 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -207,8 +207,6 @@ public: return isLegalMaskedGather(Ty, Alignment); } - unsigned maxLegalDivRemBitWidth() const { return 64; } - InstructionCost getMemcpyCost(const Instruction *I); int getNumMemOps(const IntrinsicInst *I) const; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d31d175..cfbef84 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -170,6 +170,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, if (!Subtarget.canUseCMPXCHG8B()) setMaxAtomicSizeInBitsSupported(32); + setMaxDivRemBitWidthSupported(Subtarget.is64Bit() ? 128 : 64); + // Set up the register classes. addRegisterClass(MVT::i8, &X86::GR8RegClass); addRegisterClass(MVT::i16, &X86::GR16RegClass); diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 36b7501..d967e35 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5702,10 +5702,6 @@ bool X86TTIImpl::isExpensiveToSpeculativelyExecute(const Instruction* I) { return BaseT::isExpensiveToSpeculativelyExecute(I); } -unsigned X86TTIImpl::maxLegalDivRemBitWidth() const { - return ST->is64Bit() ? 128 : 64; -} - bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return false; } diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 56cb230..808ed39 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -252,7 +252,6 @@ public: const SmallBitVector &OpcodeMask) const; bool hasDivRemOp(Type *DataType, bool IsSigned); bool isExpensiveToSpeculativelyExecute(const Instruction *I); - unsigned maxLegalDivRemBitWidth() const; bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); bool areInlineCompatible(const Function *Caller, const Function *Callee) const; diff --git a/llvm/test/Transforms/ExpandLargeDivRem/sdiv129.ll b/llvm/test/Transforms/ExpandLargeDivRem/sdiv129.ll index 15f56e6..4ddcd73 100644 --- a/llvm/test/Transforms/ExpandLargeDivRem/sdiv129.ll +++ b/llvm/test/Transforms/ExpandLargeDivRem/sdiv129.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s +; RUN: opt -S -mtriple=x86_64-- -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s define void @sdiv129(i129* %ptr, i129* %out) nounwind { ; CHECK-LABEL: @sdiv129( diff --git a/llvm/test/Transforms/ExpandLargeDivRem/srem129.ll b/llvm/test/Transforms/ExpandLargeDivRem/srem129.ll index 660c2ec..2510762 100644 --- a/llvm/test/Transforms/ExpandLargeDivRem/srem129.ll +++ b/llvm/test/Transforms/ExpandLargeDivRem/srem129.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s +; RUN: opt -S -mtriple=x86_64-- -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s define void @test(i129* %ptr, i129* %out) nounwind { ; CHECK-LABEL: @test( diff --git a/llvm/test/Transforms/ExpandLargeDivRem/udiv129.ll b/llvm/test/Transforms/ExpandLargeDivRem/udiv129.ll index 45a7f0b..31e7146 100644 --- a/llvm/test/Transforms/ExpandLargeDivRem/udiv129.ll +++ b/llvm/test/Transforms/ExpandLargeDivRem/udiv129.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s +; RUN: opt -S -mtriple=x86_64-- -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s define void @test(i129* %ptr, i129* %out) nounwind { ; CHECK-LABEL: @test( diff --git a/llvm/test/Transforms/ExpandLargeDivRem/urem129.ll b/llvm/test/Transforms/ExpandLargeDivRem/urem129.ll index d0c4ca8..9aaf136 100644 --- a/llvm/test/Transforms/ExpandLargeDivRem/urem129.ll +++ b/llvm/test/Transforms/ExpandLargeDivRem/urem129.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s +; RUN: opt -S -mtriple=x86_64-- -expand-large-div-rem -expand-div-rem-bits 128 < %s | FileCheck %s define void @test(i129* %ptr, i129* %out) nounwind { ; CHECK-LABEL: @test(