From: David Howells Date: Tue, 11 Apr 2006 05:54:24 +0000 (-0700) Subject: [PATCH] Improve data-dependency memory barrier example in documentation X-Git-Tag: accepted/tizen/common/20141203.182822~38110 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c14038c39ddd9c14225907a05a6ac4d91d645ef1;p=platform%2Fkernel%2Flinux-arm64.git [PATCH] Improve data-dependency memory barrier example in documentation In the memory barrier document, improve the example of the data dependency barrier situation by: (1) showing the initial values of the variables involved; and (2) repeating the instruction sequence description, this time with the data dependency barrier actually shown to make it clear what the revised sequence actually is. Signed-off-by: David Howells Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 528d52f..92f0056 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -610,6 +610,7 @@ loads. Consider the following sequence of events: CPU 1 CPU 2 ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } STORE A = 1 STORE B = 2 @@ -651,7 +652,20 @@ In the above example, CPU 2 perceives that B is 7, despite the load of *C (which would be B) coming after the the LOAD of C. If, however, a data dependency barrier were to be placed between the load of C -and the load of *C (ie: B) on CPU 2, then the following will occur: +and the load of *C (ie: B) on CPU 2: + + CPU 1 CPU 2 + ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } + STORE A = 1 + STORE B = 2 + + STORE C = &B LOAD X + STORE D = 4 LOAD C (gets &B) + + LOAD *C (reads B) + +then the following will occur: +-------+ : : : : | | +------+ +-------+