From: Craig Topper <craig.topper@intel.com>
Date: Fri, 20 Sep 2019 18:52:49 +0000 (+0000)
Subject: [Mips] Remove immarg test for intrinsics that no longer have an immarg after r372409.
X-Git-Tag: llvmorg-11-init~8734
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c139d1e28109450085a11e3b2ec7d53c6a00c37b;p=platform%2Fupstream%2Fllvm.git

[Mips] Remove immarg test for intrinsics that no longer have an immarg after r372409.

llvm-svn: 372420
---

diff --git a/llvm/test/Verifier/Mips/intrinsic-immarg.ll b/llvm/test/Verifier/Mips/intrinsic-immarg.ll
deleted file mode 100644
index dfe5aa9..0000000
--- a/llvm/test/Verifier/Mips/intrinsic-immarg.ll
+++ /dev/null
@@ -1,82 +0,0 @@
-; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
-
-define void @ld_b(<16 x i8> * %ptr, i8 * %ldptr, i32 %offset) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: %a = call <16 x i8> @llvm.mips.ld.b(i8* %ldptr, i32 %offset)
-  %a = call <16 x i8> @llvm.mips.ld.b(i8* %ldptr, i32 %offset)
-  store <16 x i8> %a, <16 x i8> * %ptr, align 16
-  ret void
-}
-
-define void @st_b(<16 x i8> * %ptr, i8 * %ldptr, i32 %offset, i8 * %stptr) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: call void @llvm.mips.st.b(<16 x i8> %a, i8* %stptr, i32 %offset)
-  %a = call <16 x i8> @llvm.mips.ld.b(i8* %ldptr, i32 0)
-  call void @llvm.mips.st.b(<16 x i8> %a, i8* %stptr, i32 %offset)
-  ret void
-}
-
-define void @ld_w(<4 x i32> * %ptr, i8 * %ldptr, i32 %offset) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: %a = call <4 x i32> @llvm.mips.ld.w(i8* %ldptr, i32 %offset)
-  %a = call <4 x i32> @llvm.mips.ld.w(i8* %ldptr, i32 %offset)
-  store <4 x i32> %a, <4 x i32> * %ptr, align 16
-  ret void
-}
-
-define void @st_w(<8 x i16> * %ptr, i8 * %ldptr, i32 %offset, i8 * %stptr) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: call void @llvm.mips.st.w(<4 x i32> %a, i8* %stptr, i32 %offset)
-  %a = call <4 x i32> @llvm.mips.ld.w(i8* %ldptr, i32 0)
-  call void @llvm.mips.st.w(<4 x i32> %a, i8* %stptr, i32 %offset)
-  ret void
-}
-
-define void @ld_h(<8 x i16> * %ptr, i8 * %ldptr, i32 %offset) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: %a = call <8 x i16> @llvm.mips.ld.h(i8* %ldptr, i32 %offset)
-  %a = call <8 x i16> @llvm.mips.ld.h(i8* %ldptr, i32 %offset)
-  store <8 x i16> %a, <8 x i16> * %ptr, align 16
-  ret void
-}
-
-define void @st_h(<8 x i16> * %ptr, i8 * %ldptr, i32 %offset, i8 * %stptr) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: call void @llvm.mips.st.h(<8 x i16> %a, i8* %stptr, i32 %offset)
-  %a = call <8 x i16> @llvm.mips.ld.h(i8* %ldptr, i32 0)
-  call void @llvm.mips.st.h(<8 x i16> %a, i8* %stptr, i32 %offset)
-  ret void
-}
-
-define void @ld_d(<2 x i64> * %ptr, i8 * %ldptr, i32 %offset) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: %a = call <2 x i64> @llvm.mips.ld.d(i8* %ldptr, i32 %offset)
-  %a = call <2 x i64> @llvm.mips.ld.d(i8* %ldptr, i32 %offset)
-  store <2 x i64> %a, <2 x i64> * %ptr, align 16
-  ret void
-}
-
-define void @st_d(<2 x i64> * %ptr, i8 * %ldptr, i32 %offset, i8 * %stptr) {
-  ; CHECK: immarg operand has non-immediate parameter
-  ; CHECK-NEXT: i32 %offset
-  ; CHECK-NEXT: call void @llvm.mips.st.d(<2 x i64> %a, i8* %stptr, i32 %offset)
-  %a = call <2 x i64> @llvm.mips.ld.d(i8* %ldptr, i32 0)
-  call void @llvm.mips.st.d(<2 x i64> %a, i8* %stptr, i32 %offset)
-  ret void
-}
-
-declare <16 x i8> @llvm.mips.ld.b(i8*, i32)
-declare <8 x i16> @llvm.mips.ld.h(i8*, i32)
-declare <4 x i32> @llvm.mips.ld.w(i8*, i32)
-declare <2 x i64> @llvm.mips.ld.d(i8*, i32)
-declare void @llvm.mips.st.b(<16 x i8>, i8*, i32)
-declare void @llvm.mips.st.h(<8 x i16>, i8*, i32)
-declare void @llvm.mips.st.w(<4 x i32>, i8*, i32)
-declare void @llvm.mips.st.d(<2 x i64>, i8*, i32)