From: Florian Fainelli Date: Mon, 4 Apr 2016 17:55:34 +0000 (-0700) Subject: MIPS: BMIPS: BMIPS5000 has I cache filing from D cache X-Git-Tag: v4.14-rc1~3097^2~173 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c130d2fd3d59fbd5d269f7d5827bd4ed1d94aec6;p=platform%2Fkernel%2Flinux-rpi.git MIPS: BMIPS: BMIPS5000 has I cache filing from D cache BMIPS5000 and BMIPS52000 processors have their I-cache filling from the D-cache. Since BMIPS_GENERIC does not provide (yet) a cpu-feature-overrides.h file, this was not set anywhere, so make sure the R4K cache detection takes care of that. Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13010/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index e64d595..92e54fb 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1317,6 +1317,10 @@ static void probe_pcache(void) c->icache.flags |= MIPS_CACHE_IC_F_DC; break; + case CPU_BMIPS5000: + c->icache.flags |= MIPS_CACHE_IC_F_DC; + break; + case CPU_LOONGSON2: /* * LOONGSON2 has 4 way icache, but when using indexed cache op,