From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date: Thu, 9 Feb 2023 21:55:02 +0000 (+0800)
Subject: RISC-V: Add vmv C API tests
X-Git-Tag: upstream/13.1.0~1330
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c1294253310014627d4294ae67eafef10c4c77e2;p=platform%2Fupstream%2Fgcc.git

RISC-V: Add vmv C API tests

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vmv_v_v-1.c: New test.
	* gcc.target/riscv/rvv/base/vmv_v_v-2.c: New test.
	* gcc.target/riscv/rvv/base/vmv_v_v-3.c: New test.
	* gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c: New test.
	* gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c: New test.
	* gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c: New test.
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c
new file mode 100644
index 0000000..c485b1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4(src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4(src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4(src,vl);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8(src,vl);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1(src,vl);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2(src,vl);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4(src,vl);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4(src,vl);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4(src,vl);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4(src,vl);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8(src,vl);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1(src,vl);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2(src,vl);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4(src,vl);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8(src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c
new file mode 100644
index 0000000..f276d78e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8(src,31);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4(src,31);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2(src,31);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1(src,31);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2(src,31);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4(src,31);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8(src,31);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4(src,31);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2(src,31);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1(src,31);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2(src,31);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4(src,31);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8(src,31);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2(src,31);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1(src,31);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2(src,31);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4(src,31);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8(src,31);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1(src,31);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2(src,31);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4(src,31);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8(src,31);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8(src,31);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4(src,31);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2(src,31);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1(src,31);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2(src,31);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4(src,31);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2(src,31);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1(src,31);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2(src,31);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4(src,31);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2(src,31);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1(src,31);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2(src,31);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4(src,31);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8(src,31);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1(src,31);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2(src,31);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4(src,31);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8(src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c
new file mode 100644
index 0000000..7ce80d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8(src,32);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4(src,32);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2(src,32);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1(src,32);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2(src,32);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4(src,32);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8(src,32);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4(src,32);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2(src,32);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1(src,32);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2(src,32);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4(src,32);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8(src,32);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2(src,32);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1(src,32);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2(src,32);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4(src,32);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8(src,32);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1(src,32);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2(src,32);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4(src,32);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8(src,32);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8(src,32);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4(src,32);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2(src,32);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1(src,32);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2(src,32);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4(src,32);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2(src,32);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1(src,32);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2(src,32);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4(src,32);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2(src,32);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1(src,32);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2(src,32);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4(src,32);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8(src,32);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1(src,32);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2(src,32);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4(src,32);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8(src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c
new file mode 100644
index 0000000..fdd76c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8_tu(merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4_tu(merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2_tu(merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1_tu(merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2_tu(merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4_tu(merge,src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8_tu(merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4_tu(merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2_tu(merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1_tu(merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2_tu(merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4_tu(merge,src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8_tu(merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2_tu(merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1_tu(merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2_tu(merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4_tu(merge,src,vl);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8_tu(merge,src,vl);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1_tu(merge,src,vl);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2_tu(merge,src,vl);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4_tu(merge,src,vl);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8_tu(merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8_tu(merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4_tu(merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2_tu(merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1_tu(merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2_tu(merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4_tu(merge,src,vl);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8_tu(merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4_tu(merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2_tu(merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1_tu(merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2_tu(merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4_tu(merge,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8_tu(merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2_tu(merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1_tu(merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2_tu(merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4_tu(merge,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8_tu(merge,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1_tu(merge,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2_tu(merge,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4_tu(merge,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8_tu(merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c
new file mode 100644
index 0000000..74e3453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8_tu(merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4_tu(merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2_tu(merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1_tu(merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2_tu(merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4_tu(merge,src,31);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8_tu(merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4_tu(merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2_tu(merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1_tu(merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2_tu(merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4_tu(merge,src,31);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8_tu(merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2_tu(merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1_tu(merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2_tu(merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4_tu(merge,src,31);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8_tu(merge,src,31);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1_tu(merge,src,31);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2_tu(merge,src,31);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4_tu(merge,src,31);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8_tu(merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8_tu(merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4_tu(merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2_tu(merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1_tu(merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2_tu(merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4_tu(merge,src,31);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8_tu(merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4_tu(merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2_tu(merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1_tu(merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2_tu(merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4_tu(merge,src,31);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8_tu(merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2_tu(merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1_tu(merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2_tu(merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4_tu(merge,src,31);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8_tu(merge,src,31);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1_tu(merge,src,31);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2_tu(merge,src,31);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4_tu(merge,src,31);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8_tu(merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c
new file mode 100644
index 0000000..9ff1d6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf8_tu(merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf4_tu(merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8mf2_tu(merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m1_tu(merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m2_tu(merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m4_tu(merge,src,32);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i8m8_tu(merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf4_tu(merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16mf2_tu(merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m1_tu(merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m2_tu(merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m4_tu(merge,src,32);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i16m8_tu(merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32mf2_tu(merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m1_tu(merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m2_tu(merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m4_tu(merge,src,32);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i32m8_tu(merge,src,32);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m1_tu(merge,src,32);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m2_tu(merge,src,32);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m4_tu(merge,src,32);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_i64m8_tu(merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf8_tu(merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf4_tu(merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8mf2_tu(merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m1_tu(merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m2_tu(merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m4_tu(merge,src,32);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u8m8_tu(merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf4_tu(merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16mf2_tu(merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m1_tu(merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m2_tu(merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m4_tu(merge,src,32);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u16m8_tu(merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32mf2_tu(merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m1_tu(merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m2_tu(merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m4_tu(merge,src,32);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u32m8_tu(merge,src,32);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m1_tu(merge,src,32);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m2_tu(merge,src,32);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m4_tu(merge,src,32);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vmv_v_v_u64m8_tu(merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */