From: Kazu Hirata Date: Tue, 1 Aug 2000 03:05:52 +0000 (+0000) Subject: * h8300.md: Fix formatting. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c127c1274ff15e01fa10b3221a68522a644e0bfa;p=platform%2Fupstream%2Fgcc.git * h8300.md: Fix formatting. From-SVN: r35397 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d318908..8adb971 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -130,6 +130,8 @@ 2000-07-31 Kazu Hirata + * h8300.md: Fix formatting. + * local-alloc.c: Fix formatting. * h8300.c (get_shift_alg): Remove the variable alg. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index e340d94..1f9f17f 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -66,7 +66,7 @@ ;; The size of instructions in bytes. -(define_attr "length" "" +(define_attr "length" "" (cond [(eq_attr "type" "branch") (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -120)) @@ -165,7 +165,7 @@ [(const_int 2) (const_int 2) (const_int 2) (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))]) (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")]) - + ;; movhi ;; ??? We use push.l on the h8300h to push a 16bit value?!? We have @@ -290,21 +290,20 @@ case 0: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; case 1: - if (REGNO(operands[0]) < REGNO(operands[1])) + if (REGNO (operands[0]) < REGNO (operands[1])) return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; - else + else return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; case 2: /* Make sure we don't trample the register we index with. */ - - if (GET_CODE(operands[1]) == MEM) + if (GET_CODE (operands[1]) == MEM) { rtx inside = XEXP (operands[1],0); - if (REG_P (inside)) + if (REG_P (inside)) { - rn = REGNO(inside); + rn = REGNO (inside); } - else if (GET_CODE (inside) == PLUS) + else if (GET_CODE (inside) == PLUS) { rtx lhs = XEXP (inside,0); rtx rhs = XEXP (inside,1); @@ -312,26 +311,26 @@ if (REG_P (rhs)) rn = REGNO (rhs); } } - if (rn == REGNO (operands[0])) + if (rn == REGNO (operands[0])) { /* Move the second word first. */ return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; } - else + else { /* See if either half is zero. If so, use sub.w to clear that half. */ - if (GET_CODE (operands[1]) == CONST_INT) - { - if ((INTVAL (operands[1]) & 0xffff) == 0) - return \"mov.w %e1,%e0\;sub.w %f0,%f0\"; - if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0) - return \"sub.w %e0,%e0\;mov.w %f1,%f0\"; - } - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + if (GET_CODE (operands[1]) == CONST_INT) + { + if ((INTVAL (operands[1]) & 0xffff) == 0) + return \"mov.w %e1,%e0\;sub.w %f0,%f0\"; + if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0) + return \"sub.w %e0,%e0\;mov.w %f1,%f0\"; + } + return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; } case 3: - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 4: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; case 5: @@ -351,28 +350,27 @@ || register_operand (operands[1], SFmode))" "* { - /* Copy of the movsi stuff */ + /* Copy of the movsi stuff. */ int rn = -1; switch (which_alternative) { case 0: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; case 1: - if (REGNO(operands[0]) < REGNO(operands[1])) + if (REGNO (operands[0]) < REGNO (operands[1])) return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; - else + else return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; case 2: /* Make sure we don't trample the register we index with. */ - - if (GET_CODE (operands[1]) == MEM) + if (GET_CODE (operands[1]) == MEM) { rtx inside = XEXP (operands[1],0); if (REG_P (inside)) { rn = REGNO (inside); } - else if (GET_CODE (inside) == PLUS) + else if (GET_CODE (inside) == PLUS) { rtx lhs = XEXP (inside,0); rtx rhs = XEXP (inside,1); @@ -381,15 +379,12 @@ } } if (rn == REGNO (operands[0])) - { - /* move the second word first */ - return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; - } - else - { - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; - } - + /* Move the second word first. */ + return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; + else + /* Move the first word first. */ + return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + case 3: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 4: @@ -430,13 +425,13 @@ number to zero in one of the two low bytes. */ if (val == (val & 0xff)) { - operands[1] = GEN_INT ((char)val & 0xff); + operands[1] = GEN_INT ((char) val & 0xff); return \"sub.l %S0,%S0\;add.b %1,%w0\"; } - + if (val == (val & 0xff00)) { - operands[1] = GEN_INT ((char)(val >> 8) & 0xff); + operands[1] = GEN_INT ((char) (val >> 8) & 0xff); return \"sub.l %S0,%S0\;add.b %1,%x0\"; } @@ -509,7 +504,7 @@ "btst %Z1,%R0" [(set_attr "length" "2") (set_attr "cc" "set_zn")]) - + (define_insn "" [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r") (const_int 1) @@ -626,7 +621,7 @@ "@ adds %2,%A0 subs %G2,%A0 - add.b %s2,%s0\;addx %t2,%t0 + add.b %s2,%s0\;addx %t2,%t0 add.w %T2,%T0 mov.w %T1,%T0\;add.w %T2,%T0" [(set_attr "length" "2,2,4,2,6") @@ -978,9 +973,9 @@ { int i = INTVAL (operands[2]); - if ((i & 0x00ff) != 0x00ff) + if ((i & 0x00ff) != 0x00ff) output_asm_insn (\"and %s2,%s0\", operands); - if ((i & 0xff00) != 0xff00) + if ((i & 0xff00) != 0xff00) output_asm_insn (\"and %t2,%t0\", operands); return \"\"; } @@ -1031,9 +1026,9 @@ output_asm_insn (\"and %w2,%w0\", operands); if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared) output_asm_insn (\"and %x2,%x0\", operands); - if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared) + if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared) output_asm_insn (\"and %y2,%y0\", operands); - if ((i & 0xff000000) != 0xff000000 && !upper_cleared) + if ((i & 0xff000000) != 0xff000000 && !upper_cleared) output_asm_insn (\"and %z2,%z0\", operands); return \"\"; } @@ -1083,9 +1078,9 @@ { int i = INTVAL (operands[2]); - if ((i & 0x00ff) != 0) + if ((i & 0x00ff) != 0) output_asm_insn (\"or %s2,%s0\", operands); - if ((i & 0xff00) != 0) + if ((i & 0xff00) != 0) output_asm_insn (\"or %t2,%t0\", operands); return \"\"; } @@ -1114,14 +1109,14 @@ if ((TARGET_H8300H || TARGET_H8300S) && (i & 0xffff0000) != 0x00000000) return \"or.l %S2,%S0\"; - - if ((i & 0x000000ff) != 0) + + if ((i & 0x000000ff) != 0) output_asm_insn (\"or %w2,%w0\", operands); - if ((i & 0x0000ff00) != 0) + if ((i & 0x0000ff00) != 0) output_asm_insn (\"or %x2,%x0\", operands); - if ((i & 0x00ff0000) != 0) + if ((i & 0x00ff0000) != 0) output_asm_insn (\"or %y2,%y0\", operands); - if ((i & 0xff000000) != 0) + if ((i & 0xff000000) != 0) output_asm_insn (\"or %z2,%z0\", operands); return \"\"; } @@ -1170,9 +1165,9 @@ { int i = INTVAL (operands[2]); - if ((i & 0x00ff) != 0) + if ((i & 0x00ff) != 0) output_asm_insn (\"xor %s2,%s0\", operands); - if ((i & 0xff00) != 0) + if ((i & 0xff00) != 0) output_asm_insn (\"xor %t2,%t0\", operands); return \"\"; } @@ -1202,13 +1197,13 @@ && (i & 0xffff0000) != 0x00000000) return \"xor.l %S2,%S0\"; - if ((i & 0x000000ff) != 0) + if ((i & 0x000000ff) != 0) output_asm_insn (\"xor %w2,%w0\", operands); - if ((i & 0x0000ff00) != 0) + if ((i & 0x0000ff00) != 0) output_asm_insn (\"xor %x2,%x0\", operands); - if ((i & 0x00ff0000) != 0) + if ((i & 0x00ff0000) != 0) output_asm_insn (\"xor %y2,%y0\", operands); - if ((i & 0xff000000) != 0) + if ((i & 0xff000000) != 0) output_asm_insn (\"xor %z2,%z0\", operands); return \"\"; } @@ -1338,7 +1333,6 @@ (const_int 0)) (const_int 8) (const_int 2)))]) - ;; ---------------------------------------------------------------------- ;; JUMP INSTRUCTIONS @@ -1455,13 +1449,13 @@ return 0; } - if (get_attr_length (insn) == 2) + if (get_attr_length (insn) == 2) return \"b%j1 %l0\"; - else if (get_attr_length (insn) == 4) + else if (get_attr_length (insn) == 4) return \"b%j1 %l0:16\"; else return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; -}" +}" [(set_attr "type" "branch") (set_attr "cc" "none")]) @@ -1484,9 +1478,9 @@ return 0; } - if (get_attr_length (insn) == 2) + if (get_attr_length (insn) == 2) return \"b%k1 %l0\"; - else if (get_attr_length (insn) == 4) + else if (get_attr_length (insn) == 4) return \"b%k1 %l0:16\"; else return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; @@ -1656,7 +1650,7 @@ (define_expand "zero_extendhisi2_h8300" [(set (reg:HI 1) (match_operand:HI 1 "general_operand" "")) (set (reg:SI 0) (zero_extend:SI (reg:HI 1))) - (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))] + (set (match_operand:SI 0 "general_operand" "") (reg:SI 0))] "TARGET_H8300" "") @@ -1740,7 +1734,7 @@ (define_expand "extendhisi2_h8300" [(set (reg:HI 1) (match_operand:HI 1 "general_operand" "")) (set (reg:SI 0) (sign_extend:SI (reg:HI 1))) - (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))] + (set (match_operand:SI 0 "general_operand" "") (reg:SI 0))] "TARGET_H8300" "") @@ -1808,7 +1802,7 @@ (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r,r") - (match_operator:QI 3 "nshift_operator" + (match_operator:QI 3 "nshift_operator" [ (match_operand:QI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "KM,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] @@ -1842,7 +1836,7 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI 3 "nshift_operator" + (match_operator:HI 3 "nshift_operator" [ (match_operand:HI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "KM,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] @@ -1879,7 +1873,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI 3 "nshift_operator" + (match_operator:SI 3 "nshift_operator" [ (match_operand:SI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "K,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] @@ -1896,14 +1890,14 @@ ;; You'll never believe all these patterns perform one basic action -- ;; load a bit from the source, optionally invert the bit, then store it -;; in the destination (which is known to be zero).. +;; in the destination (which is known to be zero). ;; ;; Combine obviously need some work to better identify this situation and ;; canonicalize the form better. -;; +;; ;; Normal loads with a 16bit destination. -;; +;; ;; Yes, both cases are needed. ;; (define_insn "" @@ -1927,9 +1921,9 @@ [(set_attr "cc" "clobber") (set_attr "length" "6")]) -;; +;; ;; Inverted loads with a 16bit destination. -;; +;; ;; Yes, all four cases are needed. ;; @@ -1946,7 +1940,7 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=&r") - (and:HI (not:HI + (and:HI (not:HI (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur") (match_operand:HI 2 "const_int_operand" "n"))) @@ -1958,8 +1952,8 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=&r") - (and:HI (not:HI - (subreg:HI + (and:HI (not:HI + (subreg:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Ur") (match_operand:SI 2 "const_int_operand" "n")) 1)) @@ -1971,8 +1965,8 @@ (define_insn "" [(set (match_operand:HI 0 "register_operand" "=&r") - (and:HI (not:HI - (subreg:HI + (and:HI (not:HI + (subreg:HI (lshiftrt:SI (match_operand:SI 1 "bit_operand" "Ur") (match_operand:SI 2 "const_int_operand" "n")) 0)) @@ -1983,9 +1977,9 @@ [(set_attr "cc" "clobber") (set_attr "length" "8")]) -;; +;; ;; Normal loads with a 32bit destination. -;; +;; ;; Yes, all three cases are needed. ;; (define_insn "" @@ -2004,7 +1998,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&r") - (and:SI (zero_extend:SI + (and:SI (zero_extend:SI (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur") (match_operand:QI 2 "const_int_operand" "n"))) @@ -2020,7 +2014,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&r") - (and:SI (zero_extend:SI + (and:SI (zero_extend:SI (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur") (match_operand:HI 2 "const_int_operand" "n"))) @@ -2034,9 +2028,9 @@ (const_int 10) (const_int 8)))]) -;; +;; ;; Inverted loads with a 32bit destination. -;; +;; ;; Yes, all seven cases are needed. ;; (define_insn "" @@ -2100,7 +2094,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&r") (and:SI (not:SI - (subreg:SI + (subreg:SI (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur") (match_operand:HI 2 "const_int_operand" "n")) 0)) @@ -2117,7 +2111,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&r") (and:SI (not:SI - (subreg:SI + (subreg:SI (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur") (match_operand:QI 2 "const_int_operand" "n")) 0)) @@ -2171,7 +2165,7 @@ (set_attr "length" "4")]) (define_expand "extzv" - [(set (match_operand:HI 0 "register_operand" "") + [(set (match_operand:HI 0 "register_operand" "") (zero_extract:HI (match_operand:HI 1 "bit_operand" "") (match_operand:HI 2 "general_operand" "") (match_operand:HI 3 "general_operand" "")))] @@ -2224,42 +2218,42 @@ ;; Notice a move which could be post incremented. -(define_peephole +(define_peephole [(set (match_operand:QI 0 "register_operand" "") (mem:QI (match_operand:HI 1 "register_operand" ""))) (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))] - "REGNO(operands[1]) != REGNO(operands[0])" + "REGNO (operands[1]) != REGNO (operands[0])" "mov.b @%T1+,%X0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) -(define_peephole +(define_peephole [(set (match_operand:HI 0 "register_operand" "") (mem:HI (match_operand:HI 1 "register_operand" ""))) (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))] - "REGNO(operands[1]) != REGNO(operands[0])" + "REGNO (operands[1]) != REGNO (operands[0])" "mov.w @%T1+,%T0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) ;; Notice a move which could be predecremented. -(define_peephole +(define_peephole [(set (match_operand:HI 1 "register_operand" "") (plus:HI (match_dup 1) (const_int -1))) (set (mem:QI (match_dup 1)) (match_operand:QI 0 "register_operand" ""))] - "REGNO(operands[1]) != REGNO(operands[0])" + "REGNO (operands[1]) != REGNO (operands[0])" "mov.b %X0,@-%T1" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) -(define_peephole +(define_peephole [(set (match_operand:HI 1 "register_operand" "") (plus:HI (match_dup 1) (const_int -2))) (set (mem:HI (match_dup 1)) (match_operand:HI 0 "register_operand" ""))] - "REGNO(operands[1]) != REGNO(operands[0])" + "REGNO (operands[1]) != REGNO (operands[0])" "mov.w %T0,@-%T1" [(set_attr "length" "2") (set_attr "cc" "set_znv")])