From: Jason Gunthorpe <jgg@nvidia.com>
Date: Thu, 13 Jan 2022 17:21:03 +0000 (-0400)
Subject: Merge tag 'v5.16' into rdma.git for-next
X-Git-Tag: v6.1-rc5~2225^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c0fe82baaeb2719f910359684c0817057f79a84a;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'v5.16' into rdma.git for-next

To resolve minor conflict in:
        drivers/infiniband/hw/mlx5/mlx5_ib.h

By merging both hunks.

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---

c0fe82baaeb2719f910359684c0817057f79a84a
diff --cc drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index e9a73c3,35c61da..12be85f
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@@ -1427,9 -1441,17 +1427,17 @@@ struct hns_roce_v2_priv 
  struct hns_roce_dip {
  	u8 dgid[GID_LEN_V2];
  	u32 dip_idx;
 -	struct list_head node;	/* all dips are on a list */
 +	struct list_head node; /* all dips are on a list */
  };
  
+ /* only for RNR timeout issue of HIP08 */
+ #define HNS_ROCE_CLOCK_ADJUST 1000
+ #define HNS_ROCE_MAX_CQ_PERIOD 65
+ #define HNS_ROCE_MAX_EQ_PERIOD 65
+ #define HNS_ROCE_RNR_TIMER_10NS 1
+ #define HNS_ROCE_1US_CFG 999
+ #define HNS_ROCE_1NS_CFG 0
+ 
  #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM	0x0
  #define HNS_ROCE_AEQ_DEFAULT_INTERVAL	0x0
  #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM	0x0
diff --cc drivers/infiniband/hw/mlx5/mlx5_ib.h
index 35d27f4,e636e95..cbc20e4
--- a/drivers/infiniband/hw/mlx5/mlx5_ib.h
+++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
@@@ -665,8 -664,9 +665,9 @@@ struct mlx5_ib_mr 
  
  	/* User MR data */
  	struct mlx5_cache_ent *cache_ent;
 +	/* Everything after cache_ent is zero'd when MR allocated */
+ 	struct ib_umem *umem;
  
 -	/* This is zero'd when the MR is allocated */
  	union {
  		/* Used only while the MR is in the cache */
  		struct {