From: Ard Biesheuvel <ardb@kernel.org>
Date: Thu, 11 Feb 2021 08:19:46 +0000 (+0100)
Subject: ARM: 9057/1: cache-v7: add missing ISB after cache level selection
X-Git-Tag: accepted/tizen/unified/20230118.172025~7276^2~14
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c0e50736e826b51ddc437e6cf0dc68f07e4ad16b;p=platform%2Fkernel%2Flinux-rpi.git

ARM: 9057/1: cache-v7: add missing ISB after cache level selection

A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index dc8f152..307f381 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -38,9 +38,10 @@ icache_size:
  * procedures.
  */
 ENTRY(v7_invalidate_l1)
-       mov     r0, #0
-       mcr     p15, 2, r0, c0, c0, 0
-       mrc     p15, 1, r0, c0, c0, 0
+	mov	r0, #0
+	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
+	isb
+	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
 
        movw    r1, #0x7fff
        and     r2, r1, r0, lsr #13