From: Samuel Pitoiset Date: Wed, 2 Nov 2022 10:27:13 +0000 (+0100) Subject: radv: invalidate L2 instead of only writeback L2 when using DCC stores X-Git-Tag: upstream/22.3.5~503 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c0c453e5ca640d386c06f296b06549245c20fa19;p=platform%2Fupstream%2Fmesa.git radv: invalidate L2 instead of only writeback L2 when using DCC stores It seems INV_L2 is the right thing to do, especially for RDNA2 chips with non-coherent RBs (NAVI22 is one of these). This fixes DCC corruption. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6476 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7507 Cc: mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: (cherry picked from commit 06adf6ad117e92a832c5073326bd83b638b3ca37) --- diff --git a/.pick_status.json b/.pick_status.json index ca9b4b7..d35bef9 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1273,7 +1273,7 @@ "description": "radv: invalidate L2 instead of only writeback L2 when using DCC stores", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ab72186..90fa226 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4574,11 +4574,8 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 src_fla } } - /* This is valid even for the rb_noncoherent_dirty case, because with how we account for - * dirtyness, if it isn't dirty it doesn't contain the data at all and hence doesn't need - * invalidating. */ if (!image_is_coherent) - flush_bits |= RADV_CMD_FLAG_WB_L2; + flush_bits |= RADV_CMD_FLAG_INV_L2; break; case VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR: case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT: