From: Krzysztof Parzyszek Date: Sun, 13 Nov 2022 21:10:06 +0000 (-0600) Subject: [Hexagon] Use `Register` instead of `unsigned`, NFC X-Git-Tag: upstream/17.0.6~27808 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c0abd057102836e5a32d1b02e0367cb2c9993672;p=platform%2Fupstream%2Fllvm.git [Hexagon] Use `Register` instead of `unsigned`, NFC Use `Register` instead of `unsigned` in HexagonInstrInfo, HexagonRegisterInfo, HexagonFrameLowering, and HexagonHardwareLoops. --- diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index e744a52..36b7376 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -246,13 +246,13 @@ FunctionPass *llvm::createHexagonCallFrameInformation() { /// Map a register pair Reg to the subregister that has the greater "number", /// i.e. D3 (aka R7:6) will be mapped to R7, etc. -static unsigned getMax32BitSubRegister(unsigned Reg, +static Register getMax32BitSubRegister(Register Reg, const TargetRegisterInfo &TRI, bool hireg = true) { if (Reg < Hexagon::D0 || Reg > Hexagon::D15) return Reg; - unsigned RegNo = 0; + Register RegNo = 0; for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { if (hireg) { if (*SubRegs > RegNo) @@ -266,16 +266,16 @@ static unsigned getMax32BitSubRegister(unsigned Reg, } /// Returns the callee saved register with the largest id in the vector. -static unsigned getMaxCalleeSavedReg(ArrayRef CSI, +static Register getMaxCalleeSavedReg(ArrayRef CSI, const TargetRegisterInfo &TRI) { static_assert(Hexagon::R1 > 0, "Assume physical registers are encoded as positive integers"); if (CSI.empty()) return 0; - unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI); + Register Max = getMax32BitSubRegister(CSI[0].getReg(), TRI); for (unsigned I = 1, E = CSI.size(); I < E; ++I) { - unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI); + Register Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI); if (Reg > Max) Max = Reg; } @@ -610,7 +610,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, // Get the number of bytes to allocate from the FrameInfo. unsigned NumBytes = MFI.getStackSize(); - unsigned SP = HRI.getStackRegister(); + Register SP = HRI.getStackRegister(); unsigned MaxCF = MFI.getMaxCallFrameSize(); MachineBasicBlock::iterator InsertPt = MBB.begin(); @@ -687,7 +687,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, break; } - unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3 + Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3 : Hexagon::R6; int LoadStoreCount = ObjSize / OpcodeChecker; @@ -766,7 +766,7 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { auto &HST = MF.getSubtarget(); auto &HII = *HST.getInstrInfo(); auto &HRI = *HST.getRegisterInfo(); - unsigned SP = HRI.getStackRegister(); + Register SP = HRI.getStackRegister(); MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator(); DebugLoc dl = MBB.findDebugLoc(InsertPt); @@ -899,7 +899,7 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, MachineMemOperand::MOStore, 4, Align(4)); DebugLoc dl = MBB.findDebugLoc(InsertPt); - unsigned SP = HRI.getStackRegister(); + Register SP = HRI.getStackRegister(); if (NumBytes >= ALLOCFRAME_MAX) { // Emit allocframe(#0). @@ -910,7 +910,7 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, .addMemOperand(MMO); // Subtract the size from the stack pointer. - unsigned SP = HRI.getStackRegister(); + Register SP = HRI.getStackRegister(); BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) .addReg(SP) .addImm(-int(NumBytes)); @@ -1074,7 +1074,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB, .addCFIIndex(MF.addFrameInst(OffR30)); } - static unsigned int RegsToMove[] = { + static Register RegsToMove[] = { Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2, Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22, @@ -1087,7 +1087,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB, const std::vector &CSI = MFI.getCalleeSavedInfo(); for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) { - unsigned Reg = RegsToMove[i]; + Register Reg = RegsToMove[i]; auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool { return C.getReg() == Reg; }; @@ -1189,7 +1189,7 @@ enum SpillKind { SK_FromMemTailcall }; -static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, +static const char *getSpillFunctionFor(Register MaxReg, SpillKind SpillType, bool Stkchk = false) { const char * V4SpillToMemoryFunctions[] = { "__save_r16_through_r17", @@ -1375,7 +1375,7 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB, if (useSpillFunction(MF, CSI)) { PrologueStubs = true; - unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI); + Register MaxReg = getMaxCalleeSavedReg(CSI, HRI); bool StkOvrFlowEnabled = EnableStackOVFSanitizer; const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem, StkOvrFlowEnabled); @@ -1441,7 +1441,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB, if (useRestoreFunction(MF, CSI)) { bool HasTC = hasTailCall(MBB) || !hasReturn(MBB); - unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI); + Register MaxR = getMaxCalleeSavedReg(CSI, HRI); SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem; const char *RestoreFn = getSpillFunctionFor(MaxR, Kind); auto &HTM = static_cast(MF.getTarget()); @@ -1571,7 +1571,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized( } // Set the physical aligned-stack base address register. - unsigned AP = 0; + Register AP = 0; if (const MachineInstr *AI = getAlignaInstr(MF)) AP = AI->getOperand(0).getReg(); auto &HMFI = *MF.getInfo(); @@ -1583,7 +1583,7 @@ static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { MachineRegisterInfo &MRI = MF.getRegInfo(); - auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool { + auto IsUsed = [&HRI,&MRI] (Register Reg) -> bool { for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI) if (MRI.isPhysRegUsed(*AI)) return true; @@ -1604,7 +1604,7 @@ static bool needToReserveScavengingSpillSlots(MachineFunction &MF, static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { - unsigned R = x; + Register R = x; dbgs() << ' ' << printReg(R, &TRI); } dbgs() << " }"; @@ -1638,7 +1638,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // sub- and super-registers from SRegs. BitVector Reserved = TRI->getReservedRegs(MF); for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) { - unsigned R = x; + Register R = x; for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = false; } @@ -1653,12 +1653,12 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.) BitVector TmpSup(Hexagon::NUM_TARGET_REGS); for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { - unsigned R = x; + Register R = x; for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) TmpSup[*SR] = true; } for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) { - unsigned R = x; + Register R = x; for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) { if (!Reserved[*SR]) continue; @@ -1677,7 +1677,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // (5) For each register R in SRegs, if any super-register of R is in SRegs, // remove R from SRegs. for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { - unsigned R = x; + Register R = x; for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) { if (!SRegs[*SR]) continue; @@ -1711,7 +1711,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // we need to store R0-R3 in functions with exception handling. For each // such register, create a non-fixed stack object. for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { - unsigned R = x; + Register R = x; const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); unsigned Size = TRI->getSpillSize(*RC); int Off = MinOffset - Size; @@ -1740,7 +1740,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // Verify that all registers were handled. bool MissedReg = false; for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { - unsigned R = x; + Register R = x; dbgs() << printReg(R, TRI) << ' '; MissedReg = true; } @@ -1753,7 +1753,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineInstr *MI = &*It; DebugLoc DL = MI->getDebugLoc(); Register DstR = MI->getOperand(0).getReg(); @@ -1774,7 +1774,7 @@ bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B, bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; @@ -1807,7 +1807,7 @@ bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B, bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; @@ -1838,7 +1838,7 @@ bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B, bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; @@ -1875,7 +1875,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; @@ -1910,7 +1910,7 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); @@ -1975,7 +1975,7 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); @@ -2021,7 +2021,7 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; @@ -2052,7 +2052,7 @@ bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B, bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, - const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { + const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; @@ -2080,7 +2080,7 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, } bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, - SmallVectorImpl &NewRegs) const { + SmallVectorImpl &NewRegs) const { auto &HII = *MF.getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); bool Changed = false; @@ -2138,7 +2138,7 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, SavedRegs.set(*R); // Replace predicate register pseudo spill code. - SmallVector NewRegs; + SmallVector NewRegs; expandSpillMacros(MF, NewRegs); if (OptimizeSpillSlots && !isOptNone(MF)) optimizeSpillSlots(MF, NewRegs); @@ -2153,7 +2153,7 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, // the stack offset in case it does not fit into a spill instruction. SpillRCs.insert(&Hexagon::IntRegsRegClass); - for (unsigned VR : NewRegs) + for (Register VR : NewRegs) SpillRCs.insert(MRI.getRegClass(VR)); for (const auto *RC : SpillRCs) { @@ -2180,7 +2180,7 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); } -unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF, +Register HexagonFrameLowering::findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR, HexagonBlockRanges::InstrIndexMap &IndexMap, HexagonBlockRanges::RegToRangeMap &DeadMap, @@ -2188,7 +2188,7 @@ unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF, auto &HRI = *MF.getSubtarget().getRegisterInfo(); auto &MRI = MF.getRegInfo(); - auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool { + auto isDead = [&FIR,&DeadMap] (Register Reg) -> bool { auto F = DeadMap.find({Reg,0}); if (F == DeadMap.end()) return false; @@ -2198,7 +2198,7 @@ unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF, return false; }; - for (unsigned Reg : RC->getRawAllocationOrder(MF)) { + for (Register Reg : RC->getRawAllocationOrder(MF)) { bool Dead = true; for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) { if (isDead(R.Reg)) @@ -2213,7 +2213,7 @@ unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF, } void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, - SmallVectorImpl &VRegs) const { + SmallVectorImpl &VRegs) const { auto &HST = MF.getSubtarget(); auto &HII = *HST.getInstrInfo(); auto &HRI = *HST.getRegisterInfo(); @@ -2461,7 +2461,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, SrcOp.getSubReg() }; auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); // The this-> is needed to unconfuse MSVC. - unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); + Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC); LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n'); if (FoundR == 0) @@ -2535,7 +2535,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } void HexagonFrameLowering::expandAlloca(MachineInstr *AI, - const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const { + const HexagonInstrInfo &HII, Register SP, unsigned CF) const { MachineBasicBlock &MB = *AI->getParent(); DebugLoc DL = AI->getDebugLoc(); unsigned A = AI->getOperand(2).getImm(); @@ -2557,7 +2557,7 @@ void HexagonFrameLowering::expandAlloca(MachineInstr *AI, MachineOperand &RdOp = AI->getOperand(0); MachineOperand &RsOp = AI->getOperand(1); - unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); + Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); // Rd = sub(r29, Rs) BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd) diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h index 7dacd87..b2222f0 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -114,7 +114,7 @@ private: using CSIVect = std::vector; void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII, - unsigned SP, unsigned CF) const; + Register SP, unsigned CF) const; void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const; void insertEpilogueInBlock(MachineBasicBlock &MBB) const; void insertAllocframe(MachineBasicBlock &MBB, @@ -131,40 +131,40 @@ private: bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; bool expandSpillMacros(MachineFunction &MF, - SmallVectorImpl &NewRegs) const; + SmallVectorImpl &NewRegs) const; - unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR, + Register findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR, HexagonBlockRanges::InstrIndexMap &IndexMap, HexagonBlockRanges::RegToRangeMap &DeadMap, const TargetRegisterClass *RC) const; void optimizeSpillSlots(MachineFunction &MF, - SmallVectorImpl &VRegs) const; + SmallVectorImpl &VRegs) const; void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 7577720..482f6d2 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -124,7 +124,7 @@ namespace { } private: - using LoopFeederMap = std::map; + using LoopFeederMap = std::map; /// Kinds of comparisons in the compare instructions. struct Comparison { @@ -180,7 +180,7 @@ namespace { /// if (R.next < #N) goto loop /// IVBump is the immediate value added to R, and IVOp is the instruction /// "R.next = R + #bump". - bool findInductionRegister(MachineLoop *L, unsigned &Reg, + bool findInductionRegister(MachineLoop *L, Register &Reg, int64_t &IVBump, MachineInstr *&IVOp) const; /// Return the comparison kind for the specified opcode. @@ -203,7 +203,7 @@ namespace { /// or a register), the function will attempt to insert computation of it /// to the loop's preheader. CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start, - const MachineOperand *End, unsigned IVReg, + const MachineOperand *End, Register IVReg, int64_t IVBump, Comparison::Kind Cmp) const; /// Return true if the instruction is not valid within a hardware @@ -320,15 +320,17 @@ namespace { private: CountValueType Kind; union Values { + Values() : R{Register(), 0} {} + Values(const Values&) = default; struct { - unsigned Reg; + Register Reg; unsigned Sub; } R; unsigned ImmVal; } Contents; public: - explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) { + explicit CountValue(CountValueType t, Register v, unsigned u = 0) { Kind = t; if (Kind == CV_Register) { Contents.R.Reg = v; @@ -341,7 +343,7 @@ namespace { bool isReg() const { return Kind == CV_Register; } bool isImm() const { return Kind == CV_Immediate; } - unsigned getReg() const { + Register getReg() const { assert(isReg() && "Wrong CountValue accessor"); return Contents.R.Reg; } @@ -400,7 +402,7 @@ bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) { } bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, - unsigned &Reg, + Register &Reg, int64_t &IVBump, MachineInstr *&IVOp ) const { @@ -413,13 +415,13 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, // This pair represents an induction register together with an immediate // value that will be added to it in each loop iteration. - using RegisterBump = std::pair; + using RegisterBump = std::pair; // Mapping: R.next -> (R, bump), where R, R.next and bump are derived // from an induction operation // R.next = R + bump // where bump is an immediate value. - using InductionMap = std::map; + using InductionMap = std::map; InductionMap IndMap; @@ -459,7 +461,8 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, if (NotAnalyzed) return false; - unsigned PredR, PredPos, PredRegFlags; + Register PredR; + unsigned PredPos, PredRegFlags; if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) return false; @@ -592,7 +595,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, if (!ExitingBlock) return nullptr; - unsigned IVReg = 0; + Register IVReg = 0; int64_t IVBump = 0; MachineInstr *IVOp; bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp); @@ -645,7 +648,8 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, // If TB is not the header, it means that the "not-taken" path must lead // to the header. bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header); - unsigned PredReg, PredPos, PredRegFlags; + Register PredReg; + unsigned PredPos, PredRegFlags; if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) return nullptr; MachineInstr *CondI = MRI->getVRegDef(PredReg); @@ -725,7 +729,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, const MachineOperand *Start, const MachineOperand *End, - unsigned IVReg, + Register IVReg, int64_t IVBump, Comparison::Kind Cmp) const { // Cannot handle comparison EQ, i.e. while (A == B). @@ -884,7 +888,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, AdjV += (IVBump-1); } - unsigned R = 0, SR = 0; + Register R = 0; + unsigned SR = 0; if (Start->isReg()) { R = Start->getReg(); SR = Start->getSubReg(); @@ -900,7 +905,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass; // Compute DistR (register with the distance between Start and End). - unsigned DistR, DistSR; + Register DistR; + unsigned DistSR; // Avoid special case, where the start value is an imm(0). if (Start->isImm() && StartV == 0) { @@ -944,7 +950,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, } // From DistR, compute AdjR (register with the adjusted distance). - unsigned AdjR, AdjSR; + Register AdjR; + unsigned AdjSR; if (AdjV == 0) { AdjR = DistR; @@ -962,7 +969,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, } // From AdjR, compute CountR (register with the final count). - unsigned CountR, CountSR; + Register CountR; + unsigned CountSR; if (IVBump == 1) { CountR = AdjR; @@ -996,11 +1004,11 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, // Check if the instruction defines a hardware loop register. using namespace Hexagon; - static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; - static const unsigned Regs1[] = { LC1, SA1 }; + static const Register Regs01[] = { LC0, SA0, LC1, SA1 }; + static const Register Regs1[] = { LC1, SA1 }; auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, std::size(Regs01)) : makeArrayRef(Regs1, std::size(Regs1)); - for (unsigned R : CheckRegs) + for (Register R : CheckRegs) if (MI->modifiesRegister(R, TRI)) return true; @@ -1592,8 +1600,8 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { // These data structures follow the same concept as the corresponding // ones in findInductionRegister (where some comments are). - using RegisterBump = std::pair; - using RegisterInduction = std::pair; + using RegisterBump = std::pair; + using RegisterInduction = std::pair; using RegisterInductionSet = std::set; // Register candidates for induction variables, with their associated bumps. @@ -1687,7 +1695,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { if (!PredDef->isCompare()) return false; - SmallSet CmpRegs; + SmallSet CmpRegs; MachineOperand *CmpImmOp = nullptr; // Go over all operands to the compare and look for immediate and register diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 74cd4ce..f74c766 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -126,12 +126,12 @@ namespace HexagonFUnits { } } -static bool isIntRegForSubInst(unsigned Reg) { +static bool isIntRegForSubInst(Register Reg) { return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); } -static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { +static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) { return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); } @@ -233,7 +233,7 @@ MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB, /// This treats possible (predicated) defs as actually happening ones /// (conservatively). static inline void parseOperands(const MachineInstr &MI, - SmallVector &Defs, SmallVector &Uses) { + SmallVectorImpl &Defs, SmallVectorImpl &Uses) { Defs.clear(); Uses.clear(); @@ -755,7 +755,7 @@ public: SmallVectorImpl &Cond) override { if (TripCount == -1) { // Check if we're done with the loop. - unsigned Done = TII->createVR(MF, MVT::i1); + Register Done = TII->createVR(MF, MVT::i1); MachineInstr *NewCmp = BuildMI(&MBB, DL, TII->get(Hexagon::C2_cmpgtui), Done) .addReg(LoopCount) @@ -1052,7 +1052,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) { Register Mx = MI.getOperand(MxOp).getReg(); - unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); + Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx) .add(MI.getOperand((HasImm ? 5 : 4))); auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0)) @@ -1690,7 +1690,8 @@ bool HexagonInstrInfo::PredicateInstruction( NOp++; } - unsigned PredReg, PredRegPos, PredRegFlags; + Register PredReg; + unsigned PredRegPos, PredRegFlags; bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); (void)GotPredReg; assert(GotPredReg); @@ -1734,7 +1735,7 @@ bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI, } continue; } else if (MO.isRegMask()) { - for (unsigned PR : Hexagon::PredRegsRegClass) { + for (Register PR : Hexagon::PredRegsRegClass) { if (!MI.modifiesRegister(PR, &HRI)) continue; Pred.push_back(MO); @@ -2089,7 +2090,7 @@ HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { return makeArrayRef(Flags); } -unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const { +Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetRegisterClass *TRC; if (VT == MVT::i1) { @@ -2198,10 +2199,10 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI, return false; const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); - SmallVector DefsA; - SmallVector DefsB; - SmallVector UsesA; - SmallVector UsesB; + SmallVector DefsA; + SmallVector DefsB; + SmallVector UsesA; + SmallVector UsesB; parseOperands(ProdMI, DefsA, UsesA); parseOperands(ConsMI, DefsB, UsesB); @@ -3188,7 +3189,7 @@ bool HexagonInstrInfo::producesStall(const MachineInstr &MI, } bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI, - unsigned PredReg) const { + Register PredReg) const { for (const MachineOperand &MO : MI.operands()) { // Predicate register must be explicitly defined. if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) @@ -3385,7 +3386,7 @@ unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const { // If so, return its group. Zero otherwise. HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup( const MachineInstr &MI) const { - unsigned DstReg, SrcReg, Src1Reg, Src2Reg; + Register DstReg, SrcReg, Src1Reg, Src2Reg; switch (MI.getOpcode()) { default: @@ -3883,7 +3884,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const { // If so, return its group. Zero otherwise. HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( const MachineInstr &MI) const { - unsigned DstReg, SrcReg, Src1Reg, Src2Reg; + Register DstReg, SrcReg, Src1Reg, Src2Reg; const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); switch (MI.getOpcode()) { @@ -4510,7 +4511,7 @@ short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const { } bool HexagonInstrInfo::getPredReg(ArrayRef Cond, - unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { + Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { if (Cond.empty()) return false; assert(Cond.size() == 2); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 703a894..0106873 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -345,7 +345,7 @@ public: /// HexagonInstrInfo specifics. - unsigned createVR(MachineFunction *MF, MVT VT) const; + Register createVR(MachineFunction *MF, MVT VT) const; MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet &Visited) const; @@ -429,7 +429,7 @@ public: const MachineInstr &ConsMI) const; bool producesStall(const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII) const; - bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const; + bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const; bool PredOpcodeHasJMP_c(unsigned Opcode) const; bool predOpcodeHasNot(ArrayRef Cond) const; @@ -463,7 +463,7 @@ public: unsigned getMemAccessSize(const MachineInstr &MI) const; int getMinValue(const MachineInstr &MI) const; short getNonExtOpcode(const MachineInstr &MI) const; - bool getPredReg(ArrayRef Cond, unsigned &PredReg, + bool getPredReg(ArrayRef Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const; short getPseudoInstrPair(const MachineInstr &MI) const; short getRegForm(const MachineInstr &MI) const; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 02517d7..9ce561d 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -58,7 +58,7 @@ HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) 0/*PC*/, HwMode) {} -bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { +bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(Register R) const { return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; } @@ -386,8 +386,8 @@ bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI, // If one register is large (HvxWR) and the other is small (HvxVR), then // coalescing is ok if the large is already live across a function call, // or if the small one is not. - unsigned SmallReg = SmallSrc ? SrcReg : DstReg; - unsigned LargeReg = SmallSrc ? DstReg : SrcReg; + Register SmallReg = SmallSrc ? SrcReg : DstReg; + Register LargeReg = SmallSrc ? DstReg : SrcReg; return any_of(LIS.getInterval(LargeReg), HasCall) || !any_of(LIS.getInterval(SmallReg), HasCall); } @@ -402,12 +402,12 @@ Register HexagonRegisterInfo::getFrameRegister(const MachineFunction } -unsigned HexagonRegisterInfo::getFrameRegister() const { +Register HexagonRegisterInfo::getFrameRegister() const { return Hexagon::R30; } -unsigned HexagonRegisterInfo::getStackRegister() const { +Register HexagonRegisterInfo::getStackRegister() const { return Hexagon::R29; } @@ -447,7 +447,7 @@ HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF, return &Hexagon::IntRegsRegClass; } -unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { +Register HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { return Hexagon::R6; } diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h index b7e3b62..572da8d 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -62,8 +62,8 @@ public: // Debug information queries. Register getFrameRegister(const MachineFunction &MF) const override; - unsigned getFrameRegister() const; - unsigned getStackRegister() const; + Register getFrameRegister() const; + Register getStackRegister() const; unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const; @@ -71,13 +71,13 @@ public: const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const; - unsigned getFirstCallerSavedNonParamReg() const; + Register getFirstCallerSavedNonParamReg() const; const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const override; - bool isEHReturnCalleeSaveReg(unsigned Reg) const; + bool isEHReturnCalleeSaveReg(Register Reg) const; }; } // end namespace llvm