From: Chunfeng Yun Date: Tue, 17 Aug 2021 09:19:39 +0000 (+0800) Subject: dt-bindings: phy: mediatek: tphy: support type switch by pericfg X-Git-Tag: accepted/tizen/unified/20230118.172025~6526^2~6^2~14 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c01608b3b46bfd5285117ab2c66df7cd59b7c67d;p=platform%2Fkernel%2Flinux-rpi.git dt-bindings: phy: mediatek: tphy: support type switch by pericfg Add support type switch by pericfg register between USB3, PCIe, SATA, SGMII, this is used to replace the way through efuse or jumper. Reviewed-by: Rob Herring Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/1629191987-20774-1-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 838852c..9e6c0f4 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -201,6 +201,22 @@ patternProperties: Specify the flag to enable BC1.2 if support it type: boolean + mediatek,syscon-type: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + A phandle to syscon used to access the register of type switch, + the field should always be 3 cells long. + items: + items: + - description: + The first cell represents a phandle to syscon + - description: + The second cell represents the register offset + - description: + The third cell represents the index of config segment + enum: [0, 1, 2, 3] + required: - reg - "#phy-cells"