From: Roland Scheidegger <sroland@vmware.com>
Date: Sat, 5 Jun 2010 14:44:31 +0000 (+0200)
Subject: st/mesa: fix bug in depthstencil optimizing clear logic
X-Git-Tag: 062012170305~11988
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c00065e5c2ba8a1bcaa543b079abc883af0844f3;p=profile%2Fivi%2Fmesa.git

st/mesa: fix bug in depthstencil optimizing clear logic
---

diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c
index a819d30..b157925 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -540,7 +540,8 @@ st_Clear(GLcontext *ctx, GLbitfield mask)
        * required from the visual. Hence fix this up to avoid potential
        * read-modify-write in the driver.
        */
-      if (((clear_buffers & PIPE_CLEAR_DEPTHSTENCIL) != PIPE_CLEAR_DEPTHSTENCIL) &&
+      if ((clear_buffers & PIPE_CLEAR_DEPTHSTENCIL) &&
+          ((clear_buffers & PIPE_CLEAR_DEPTHSTENCIL) != PIPE_CLEAR_DEPTHSTENCIL) &&
           (depthRb == stencilRb) &&
           (ctx->DrawBuffer->Visual.depthBits == 0 ||
            ctx->DrawBuffer->Visual.stencilBits == 0))