From: jacquesguan Date: Tue, 8 Feb 2022 03:32:42 +0000 (+0800) Subject: [RISCV] Recover the implication between Zve* extensions and the V extension. X-Git-Tag: upstream/15.0.7~16640 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bfb4c0c37078aa5ce251752d99310ccb05e1296a;p=platform%2Fupstream%2Fllvm.git [RISCV] Recover the implication between Zve* extensions and the V extension. This revision recover the implication between Zve* extensions and the V extension. Differential Revision: https://reviews.llvm.org/D119210 --- diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index fd30551..cc51bf7 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -188,7 +188,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, if (ISAInfo->hasExtension("c")) Builder.defineMacro("__riscv_compressed"); - if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v")) + if (ISAInfo->hasExtension("zve32x")) Builder.defineMacro("__riscv_vector"); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c index 7de132e1..4436744 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c @@ -11,7 +11,7 @@ // CHECK-RV64V-NEXT: ret i32 [[CONV]] // -// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x', 'V' +// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x' int test() { return __builtin_rvv_vsetvli(1, 0, 0); diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 4b80d6da..eb718ff 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -1040,7 +1040,7 @@ void RVVEmitter::createBuiltins(raw_ostream &OS) { OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n"; OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, " - "ATTRS, \"zve32x|v\")\n"; + "ATTRS, \"zve32x\")\n"; OS << "#endif\n"; for (auto &Def : Defs) { auto P = diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 598ecea..7af375a 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -688,11 +688,9 @@ Error RISCVISAInfo::checkDependency() { bool HasE = Exts.count("e") != 0; bool HasD = Exts.count("d") != 0; bool HasF = Exts.count("f") != 0; - bool HasZve32x = Exts.count("zve32x") != 0; + bool HasVector = Exts.count("zve32x") != 0; bool HasZve32f = Exts.count("zve32f") != 0; bool HasZve64d = Exts.count("zve64d") != 0; - bool HasV = Exts.count("v") != 0; - bool HasVector = HasZve32x || HasV; bool HasZvl = MinVLen != 0; if (HasE && !IsRv32) @@ -732,7 +730,7 @@ Error RISCVISAInfo::checkDependency() { return Error::success(); } -static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"}; +static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"}; static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfh[] = {"f"}; static const char *ImpliedExtsZve64d[] = {"zve64f"}; @@ -864,11 +862,6 @@ void RISCVISAInfo::updateMaxELen() { ExtName.getAsInteger(10, ZveELen); MaxELen = std::max(MaxELen, ZveELen); } - if (ExtName == "v") { - MaxELenFp = 64; - MaxELen = 64; - return; - } } } diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index f036696..5486649 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -340,21 +340,21 @@ def FeatureStdExtZve64d def FeatureStdExtV : SubtargetFeature<"v", "HasStdExtV", "true", "'V' (Vector Extension for Application Processors)", - [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>; + [FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>; def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, AssemblerPredicate< - (any_of FeatureStdExtZve32x, FeatureStdExtV), + (any_of FeatureStdExtZve32x), "'V' (Vector Extension for Application Processors), 'Zve32x' or " "'Zve64x' (Vector Extensions for Embedded Processors)">; def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">, AssemblerPredicate< - (any_of FeatureStdExtZve64x, FeatureStdExtV), + (any_of FeatureStdExtZve64x), "'V' (Vector Extension for Application Processors) or 'Zve64x' " "(Vector Extensions for Embedded Processors)">; def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, AssemblerPredicate< - (any_of FeatureStdExtZve32f, FeatureStdExtV), + (any_of FeatureStdExtZve32f), "'V' (Vector Extension for Application Processors), 'Zve32f', " "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 7d570a4..3b5543b 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -205,19 +205,13 @@ public: } // Vector codegen related methods. - bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; } - bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; } - bool hasVInstructionsF16() const { - return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh; - } + bool hasVInstructions() const { return HasStdExtZve32x; } + bool hasVInstructionsI64() const { return HasStdExtZve64x; } + bool hasVInstructionsF16() const { return HasStdExtZve32f && HasStdExtZfh; } // FIXME: Consider Zfinx in the future - bool hasVInstructionsF32() const { - return HasStdExtV || (HasStdExtZve32f && HasStdExtF); - } + bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; } // FIXME: Consider Zdinx in the future - bool hasVInstructionsF64() const { - return HasStdExtV || (HasStdExtZve64d && HasStdExtD); - } + bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } // F16 and F64 both require F32. bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } unsigned getMaxInterleaveFactor() const { diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index b5acd9b2..a5f418f 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -85,8 +85,8 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0" ; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0" ; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0" @@ -119,8 +119,8 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0" ; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0" ; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 0ddab97..16cc49e 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -34,43 +34,43 @@ # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32iv" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl32b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl64b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl128b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl256b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl512b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl1024b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl2048b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl4096b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0" .attribute arch, "rv32ivzvl8192b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" .attribute arch, "rv32ivzvl16384b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" .attribute arch, "rv32ivzvl32768b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0" .attribute arch, "rv32ivzvl65536b" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0" .attribute arch, "rv32izve32x" # CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvl32b1p0"