From: Atish Patra Date: Fri, 22 Jul 2022 16:50:44 +0000 (-0700) Subject: RISC-V: Add SSTC extension CSR details X-Git-Tag: v6.6.17~6792^2~4^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bf952a290f7a9d818204b9b68e861655f8b15a65;p=platform%2Fkernel%2Flinux-rpi.git RISC-V: Add SSTC extension CSR details This patch just introduces the required CSR fields related to the SSTC extension. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220722165047.519994-2-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 6d85655e..34f4eaf 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -235,6 +235,9 @@ #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 #define CSR_VSTVEC 0x205 @@ -244,6 +247,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602