From: Fei Peng <fei.peng@intel.com>
Date: Mon, 12 Feb 2018 21:51:32 +0000 (-0800)
Subject: Fix SSE4.1 encoding
X-Git-Tag: accepted/tizen/unified/20190422.045933~2985
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bf6aa780a74706c2b6d1c344dff8de40a8f79f0a;p=platform%2Fupstream%2Fcoreclr.git

Fix SSE4.1 encoding
---

diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp
index 6d7a2a2..3555a0c 100644
--- a/src/jit/emitxarch.cpp
+++ b/src/jit/emitxarch.cpp
@@ -12072,21 +12072,35 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
         case IF_RWR_ARD:
         case IF_RRW_ARD:
         case IF_RWR_RRD_ARD:
-            code    = insCodeRM(ins);
-            code    = AddVexPrefixIfNeeded(ins, code, size);
-            regcode = (insEncodeReg345(ins, id->idReg1(), size, &code) << 8);
-            dst     = emitOutputAM(dst, id, code | regcode);
-            sz      = emitSizeOfInsDsc(id);
+            code = insCodeRM(ins);
+            if (Is4ByteSSE4OrAVXInstruction(ins))
+            {
+                dst = emitOutputAM(dst, id, code);
+            }
+            else
+            {
+                code    = AddVexPrefixIfNeeded(ins, code, size);
+                regcode = (insEncodeReg345(ins, id->idReg1(), size, &code) << 8);
+                dst     = emitOutputAM(dst, id, code | regcode);
+            }
+            sz = emitSizeOfInsDsc(id);
             break;
 
         case IF_RWR_RRD_ARD_CNS:
         {
             emitGetInsAmdCns(id, &cnsVal);
-            code    = insCodeRM(ins);
-            code    = AddVexPrefixIfNeeded(ins, code, size);
-            regcode = (insEncodeReg345(ins, id->idReg1(), size, &code) << 8);
-            dst     = emitOutputAM(dst, id, code | regcode, &cnsVal);
-            sz      = emitSizeOfInsDsc(id);
+            code = insCodeRM(ins);
+            if (Is4ByteSSE4OrAVXInstruction(ins))
+            {
+                dst = emitOutputAM(dst, id, code, &cnsVal);
+            }
+            else
+            {
+                code    = AddVexPrefixIfNeeded(ins, code, size);
+                regcode = (insEncodeReg345(ins, id->idReg1(), size, &code) << 8);
+                dst     = emitOutputAM(dst, id, code | regcode, &cnsVal);
+            }
+            sz = emitSizeOfInsDsc(id);
             break;
         }