From: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Mon, 12 Mar 2012 09:59:25 +0000 (+0000)
Subject: ChangeLog entry:
X-Git-Tag: upstream/12.2.0~77461
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bf2eaa3f2de7adf678876909b33bf0f7c2eb2170;p=platform%2Fupstream%2Fgcc.git

ChangeLog entry:

	  * doc/invoke.texi: Document -mrtm option.
	  * common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET):
	  New.
	  (OPTION_MASK_ISA_RTM_UNSET): Ditto.
	  (ix86_handle_option): Handle OPT_mrtm.
	  * config.gcc (i[34567]86-*-*): Add rtmintrin.h and
	  xtestintrin.h.
	  (x86_64-*-*): Ditto.
	  * i386-builtin-types.def (INT_FTYPE_VOID): New.
	  * config/i386/i386-c.c (ix86_target_macros_internal): Define
	  __RTM__ if needed.
	  (ix86_target_string): Define -mrtm option.
	  (PTA_RTM): New.
	  (ix86_option_override_internal): Extend "corei7-avx" with
	  RTM option. Handle new option.
	  (ix86_valid_target_attribute_inner_p): Add OPT_mrtm.
	  (ix86_builtins): Add IX86_BUILTIN_XBEGIN, IX86_BUILTIN_XEND,
	  IX86_BUILTIN_XTEST.
	  (bdesc_special_args): Ditto.
	  (ix86_init_mmx_sse_builtins): Add IX86_BUILTIN_XABORT.
	  (ix86_expand_special_args_builtin): Handle new built-in type.
	  (ix86_expand_builtin): Handle XABORT instruction.
	  * config/i386/i386.h (TARGET_RTM): New.
	  * config/i386/i386.md (UNSPECV_XBEGIN): New.
	  (UNSPECV_XEND): Ditto.
	  (UNSPECV_XABORT): Ditto.
	  (UNSPECV_XTEST): Ditto.
	  (xbegin): Ditto.
	  (xbegin_1): Ditto.
	  (xend): Ditto.
	  (xabort): Ditto
	  (xtest): Ditto.
	  (xtest_1): Ditto.
	  * config/i386/i386.opt (mrtm): New.
	  * config/i386/immintrin.h: Include rtmintrin.h and
	  xtestintrin.h.
	  * config/i386/rtmintrin.h: New header.
	  * config/i386/xtestintrin.h: Ditto.

testsuite/ChangeLog entry:
    * gcc.target/i386/rtm-xabort-1.c: New.
    * gcc.target/i386/rtm-xbegin-1.c: Ditto.
    * gcc.target/i386/rtm-xend-1.c: Ditto.
    * gcc.target/i386/rtm-xtest-1.c: Ditto.
    * gcc.target/i386/sse-12.c: Test RTM intrinsics.
    * gcc.target/i386/sse-13.c: Ditto.
    * gcc.target/i386/sse-14.c: Ditto.
    * gcc.target/i386/sse-22.c: Ditto.
    * gcc.target/i386/sse-23.c: Ditto.
    * g++.dg/other/i386-2.C: Ditto.
    * g++.dg/other/i386-3.C: Ditto.

From-SVN: r185218
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb0e2f1..d79f5be 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,44 @@
+2012-02-12  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	* doc/invoke.texi: Document -mrtm option.
+	* common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET):
+	New.
+	(OPTION_MASK_ISA_RTM_UNSET): Ditto.
+	(ix86_handle_option): Handle OPT_mrtm.
+	* config.gcc (i[34567]86-*-*): Add rtmintrin.h and
+	xtestintrin.h.
+	(x86_64-*-*): Ditto.
+	* i386-builtin-types.def (INT_FTYPE_VOID): New.
+	* config/i386/i386-c.c (ix86_target_macros_internal): Define
+	__RTM__ if needed.
+	(ix86_target_string): Define -mrtm option.
+	(PTA_RTM): New.
+	(ix86_option_override_internal): Extend "corei7-avx" with
+	RTM option. Handle new option.
+	(ix86_valid_target_attribute_inner_p): Add OPT_mrtm.
+	(ix86_builtins): Add IX86_BUILTIN_XBEGIN, IX86_BUILTIN_XEND,
+	IX86_BUILTIN_XTEST.
+	(bdesc_special_args): Ditto.
+	(ix86_init_mmx_sse_builtins): Add IX86_BUILTIN_XABORT.
+	(ix86_expand_special_args_builtin): Handle new built-in type.
+	(ix86_expand_builtin): Handle XABORT instruction.
+	* config/i386/i386.h (TARGET_RTM): New.
+	* config/i386/i386.md (UNSPECV_XBEGIN): New.
+	(UNSPECV_XEND): Ditto.
+	(UNSPECV_XABORT): Ditto.
+	(UNSPECV_XTEST): Ditto.
+	(xbegin): Ditto.
+	(xbegin_1): Ditto.
+	(xend): Ditto.
+	(xabort): Ditto
+	(xtest): Ditto.
+	(xtest_1): Ditto.
+	* config/i386/i386.opt (mrtm): New.
+	* config/i386/immintrin.h: Include rtmintrin.h and
+	xtestintrin.h.
+	* config/i386/rtmintrin.h: New header.
+	* config/i386/xtestintrin.h: Ditto.
+
 2012-03-12  Tristan Gingold  <gingold@adacore.com>
 
 	* ginclude/stddef.h: Adjust previous patch.  Use __VMS__ instead
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index ac4232f..70b7eb7 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -54,6 +54,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
 #define OPTION_MASK_ISA_AVX2_SET \
   (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
+#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -121,6 +122,7 @@ along with GCC; see the file COPYING3.  If not see
    | OPTION_MASK_ISA_AVX2_UNSET)
 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
 #define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
+#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -309,6 +311,19 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mrtm:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
+	}
+      return true;
+
     case OPT_msse4:
       opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
       opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 99f0b47..2ec4145 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -360,7 +360,8 @@ i[34567]86-*-*)
 		       immintrin.h x86intrin.h avxintrin.h xopintrin.h
 		       ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
 		       lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h
-		       avx2intrin.h fmaintrin.h f16cintrin.h"
+		       avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
+		       xtestintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@@ -373,7 +374,8 @@ x86_64-*-*)
 		       immintrin.h x86intrin.h avxintrin.h xopintrin.h
 		       ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
 		       lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h
-		       avx2intrin.h fmaintrin.h f16cintrin.h"
+		       avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
+		       xtestintrin.h"
 	need_64bit_hwint=yes
 	;;
 ia64-*-*)
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 5da8fd2..6696b7a 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -68,6 +68,7 @@
 #define bit_BMI		(1 << 3)
 #define bit_AVX2	(1 << 5)
 #define bit_BMI2	(1 << 8)
+#define bit_RTM		(1 << 11)
 
 #if defined(__i386__) && defined(__PIC__)
 /* %ebx may be the PIC register.  */
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index d00b053..9b3a018 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -141,6 +141,7 @@ DEF_POINTER_TYPE (PCV8SI, V8SI, CONST)
 DEF_FUNCTION_TYPE (FLOAT128)
 DEF_FUNCTION_TYPE (UINT64)
 DEF_FUNCTION_TYPE (UNSIGNED)
+DEF_FUNCTION_TYPE (INT)
 DEF_FUNCTION_TYPE (VOID)
 DEF_FUNCTION_TYPE (PVOID)
 
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index d4b0b08..8adb3b4 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -261,6 +261,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__AVX2__");
   if (isa_flag & OPTION_MASK_ISA_FMA)
     def_or_undef (parse_in, "__FMA__");
+  if (isa_flag & OPTION_MASK_ISA_RTM)
+    def_or_undef (parse_in, "__RTM__");
   if (isa_flag & OPTION_MASK_ISA_SSE4A)
     def_or_undef (parse_in, "__SSE4A__");
   if (isa_flag & OPTION_MASK_ISA_FMA4)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d673101..6744f89 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2682,6 +2682,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
     { "-mfsgsbase",	OPTION_MASK_ISA_FSGSBASE },
     { "-mrdrnd",	OPTION_MASK_ISA_RDRND },
     { "-mf16c",		OPTION_MASK_ISA_F16C },
+    { "-mrtm",		OPTION_MASK_ISA_RTM },
   };
 
   /* Flag options.  */
@@ -2930,6 +2931,7 @@ ix86_option_override_internal (bool main_args_p)
 #define PTA_XOP		 	(HOST_WIDE_INT_1 << 29)
 #define PTA_AVX2		(HOST_WIDE_INT_1 << 30)
 #define PTA_BMI2	 	(HOST_WIDE_INT_1 << 31)
+#define PTA_RTM		 	(HOST_WIDE_INT_1 << 32)
 /* if this reaches 64, need to widen struct pta flags below */
 
   static struct pta
@@ -2988,7 +2990,7 @@ ix86_option_override_internal (bool main_args_p)
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
-        | PTA_FMA | PTA_MOVBE},
+        | PTA_FMA | PTA_MOVBE | PTA_RTM},
       {"atom", PROCESSOR_ATOM, CPU_ATOM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
@@ -3355,6 +3357,9 @@ ix86_option_override_internal (bool main_args_p)
 	if (processor_alias_table[i].flags & PTA_F16C
 	    && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
 	  ix86_isa_flags |= OPTION_MASK_ISA_F16C;
+	if (processor_alias_table[i].flags & PTA_RTM
+	    && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
+	  ix86_isa_flags |= OPTION_MASK_ISA_RTM;
 	if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
 	  x86_prefetch_sse = true;
 
@@ -4155,6 +4160,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("fsgsbase",	OPT_mfsgsbase),
     IX86_ATTR_ISA ("rdrnd",	OPT_mrdrnd),
     IX86_ATTR_ISA ("f16c",	OPT_mf16c),
+    IX86_ATTR_ISA ("rtm",	OPT_mrtm),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
@@ -25643,6 +25649,12 @@ enum ix86_builtins
 
   IX86_BUILTIN_CLZS,
 
+  /* RTM */
+  IX86_BUILTIN_XBEGIN,
+  IX86_BUILTIN_XEND,
+  IX86_BUILTIN_XABORT,
+  IX86_BUILTIN_XTEST,
+
   /* BMI instructions.  */
   IX86_BUILTIN_BEXTR32,
   IX86_BUILTIN_BEXTR64,
@@ -25981,6 +25993,11 @@ static const struct builtin_description bdesc_special_args[] =
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
+
+  /* RTM */
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
 };
 
 /* Builtins with variable number of arguments.  */
@@ -27427,6 +27444,10 @@ ix86_init_mmx_sse_builtins (void)
 	       V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
 	       IX86_BUILTIN_GATHERALTDIV8SI);
 
+  /* RTM.  */
+  def_builtin (OPTION_MASK_ISA_RTM, "__builtin_ia32_xabort",
+	       VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
+
   /* MMX access to the vec_init patterns.  */
   def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si",
 		     V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
@@ -28866,6 +28887,8 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
       klass = store;
       memory = 0;
       break;
+
+    case INT_FTYPE_VOID:
     case UINT64_FTYPE_VOID:
     case UNSIGNED_FTYPE_VOID:
       nargs = 0;
@@ -29663,6 +29686,19 @@ rdrand_step:
 
       return target;
 
+    case IX86_BUILTIN_XABORT:
+      icode = CODE_FOR_xabort;
+      arg0 = CALL_EXPR_ARG (exp, 0);
+      op0 = expand_normal (arg0);
+      mode0 = insn_data[icode].operand[0].mode;
+      if (!insn_data[icode].operand[0].predicate (op0, mode0))
+	{
+	  error ("the xabort's argument must be an 8-bit immediate");
+	  return const0_rtx;
+	}
+      emit_insn (gen_xabort (op0));
+      return 0;
+
     default:
       break;
     }
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 7721c46..c77070b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -75,6 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_FSGSBASE	OPTION_ISA_FSGSBASE
 #define TARGET_RDRND	OPTION_ISA_RDRND
 #define TARGET_F16C	OPTION_ISA_F16C
+#define TARGET_RTM      OPTION_ISA_RTM
 
 #define TARGET_LP64	(TARGET_64BIT && !TARGET_X32)
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index e461512..3aac3ed 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -114,6 +114,7 @@
   UNSPEC_CALL_NEEDS_VZEROUPPER
   UNSPEC_PAUSE
   UNSPEC_LEA_ADDR
+  UNSPEC_XBEGIN_ABORT
 
   ;; For SSE/MMX support:
   UNSPEC_FIX_NOTRUNC
@@ -206,6 +207,12 @@
   UNSPECV_RDGSBASE
   UNSPECV_WRFSBASE
   UNSPECV_WRGSBASE
+
+  ;; For RTM support
+  UNSPECV_XBEGIN
+  UNSPECV_XEND
+  UNSPECV_XABORT
+  UNSPECV_XTEST
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -18196,6 +18203,72 @@
   [(set_attr "length" "2")
    (set_attr "memory" "unknown")])
 
+(define_expand "xbegin"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))]
+  "TARGET_RTM"
+{
+  rtx label = gen_label_rtx ();
+
+  operands[1] = force_reg (SImode, constm1_rtx);
+
+  emit_jump_insn (gen_xbegin_1 (operands[0], operands[1], label));
+
+  emit_label (label);
+  LABEL_NUSES (label) = 1;
+
+  DONE;
+})
+
+(define_insn "xbegin_1"
+  [(set (pc)
+	(if_then_else (ne (unspec [(const_int 0)] UNSPEC_XBEGIN_ABORT)
+			  (const_int 0))
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))
+   (set (match_operand:SI 0 "register_operand" "=a")
+	(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")]
+			    UNSPECV_XBEGIN))]
+  "TARGET_RTM"
+  "xbegin\t%l2"
+  [(set_attr "type" "other")
+   (set_attr "length" "6")])
+
+(define_insn "xend"
+  [(unspec_volatile [(const_int 0)] UNSPECV_XEND)]
+  "TARGET_RTM"
+  "xend"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
+(define_insn "xabort"
+  [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")]
+		    UNSPECV_XABORT)]
+  "TARGET_RTM"
+  "xabort\t%0"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
+(define_expand "xtest"
+  [(set (match_operand:QI 0 "register_operand" "")
+	(unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))]
+  "TARGET_RTM"
+{
+  emit_insn (gen_xtest_1 ());
+
+  ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), const0_rtx);
+
+  DONE;
+})
+
+(define_insn "xtest_1"
+  [(set (reg:CCZ FLAGS_REG)
+	(unspec_volatile:CCZ [(const_int 0)] UNSPECV_XTEST))]
+  "TARGET_RTM"
+  "xtest"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 6c516e7..1d8dc44 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -573,3 +573,7 @@ Split 32-byte AVX unaligned load
 mavx256-split-unaligned-store
 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 Split 32-byte AVX unaligned store
+
+mrtm
+Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
+Support RTM built-in functions and code generation
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 986a573d..a477f05 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -80,6 +80,14 @@
 #include <f16cintrin.h>
 #endif
 
+#ifdef __RTM__
+#include <rtmintrin.h>
+#endif
+
+#ifdef __RTM__
+#include <xtestintrin.h>
+#endif
+
 #ifdef __RDRND__
 extern __inline int
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a1196f0..096ef1f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -629,7 +629,8 @@ Objective-C and Objective-C++ Dialects}.
 -mmmx  -msse  -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
 -mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
 -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
--mbmi2 -mlwp -mthreads  -mno-align-stringops  -minline-all-stringops @gol
+-mbmi2 -mrtm -mlwp -mthreads @gol
+-mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
 -mpush-args  -maccumulate-outgoing-args  -m128bit-long-double @gol
 -m96bit-long-double  -mregparm=@var{num}  -msseregparm @gol
@@ -13605,6 +13606,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @itemx -mno-bmi2
 @itemx -mlzcnt
 @itemx -mno-lzcnt
+@itemx -mrtm
 @itemx -mtbm
 @itemx -mno-tbm
 @opindex mmmx
@@ -13615,7 +13617,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @opindex mno-3dnow
 These switches enable or disable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C,
-FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, LZCNT or 3DNow!@: 
+FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, LZCNT, RTM or 3DNow!@:
 extended instruction sets.
 These extensions are also available as built-in functions: see
 @ref{X86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cdca21e..d12b335 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2012-03-12  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	* gcc.target/i386/rtm-xabort-1.c: New.
+	* gcc.target/i386/rtm-xbegin-1.c: Ditto.
+	* gcc.target/i386/rtm-xend-1.c: Ditto.
+	* gcc.target/i386/rtm-xtest-1.c: Ditto.
+	* gcc.target/i386/sse-12.c: Test RTM intrinsics.
+	* gcc.target/i386/sse-13.c: Ditto.
+	* gcc.target/i386/sse-14.c: Ditto.
+	* gcc.target/i386/sse-22.c: Ditto.
+	* gcc.target/i386/sse-23.c: Ditto.
+	* g++.dg/other/i386-2.C: Ditto.
+	* g++.dg/other/i386-3.C: Ditto.
+
 2012-03-12  Tobias Burnus  <burnus@net-b.de>
 
 	PR fortran/52542
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index e8237a4..6800353 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index 9dd587a..b921682 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 66a36c6..1d8fc3a 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
    popcntintrin.h and mm_malloc.h are usable
    with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 4bc0a2e..a540864 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
 
 #include <mm_malloc.h>
 
@@ -180,4 +180,5 @@
 #define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1)
 #define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1)
 
-#include <x86intrin.h>
+/* rtmintrin.h */
+#define __builtin_ia32_xabort (N) __builtin_ia32_xabort (1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 6451166..a798487 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
 
 #include <mm_malloc.h>
 
@@ -19,6 +19,10 @@
 
 #define _CONCAT(x,y) x ## y
 
+#define test_0(func, type, imm)						\
+  type _CONCAT(_,func) (int const I)					\
+  { return func (imm); }
+
 #define test_1(func, type, op1_type, imm)				\
   type _CONCAT(_,func) (op1_type A, int const I)			\
   { return func (A, imm); }
@@ -95,6 +99,7 @@ test_1 (_mm256_round_ps, __m256, __m256, 1)
 test_1 (_cvtss_sh, unsigned short, float, 1)
 test_1 (_mm_cvtps_ph, __m128i, __m128, 1)
 test_1 (_mm256_cvtps_ph, __m128i, __m256, 1)
+test_0 (_xabort, void, 1)
 
 /* wmmintrin.h */
 test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 9ccb92d..50b4cc3 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -18,6 +18,10 @@
 
 #define _CONCAT(x,y) x ## y
 
+#define test_0(func, type, imm)						\
+  type _CONCAT(_,func) (int const I)					\
+  { return func (imm); }
+
 #define test_1(func, type, op1_type, imm)				\
   type _CONCAT(_,func) (op1_type A, int const I)			\
   { return func (A, imm); }
@@ -46,7 +50,7 @@
 
 
 #ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm")
 #endif
 
 /* Following intrinsics require immediate arguments.  They
@@ -159,9 +163,9 @@ test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
 test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
 test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
 
-/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C) */
+/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM) */
 #ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm")
 #endif
 #include <immintrin.h>
 test_1 (_cvtss_sh, unsigned short, float, 1)
@@ -241,6 +245,9 @@ test_2 ( _mm256_i32gather_epi32, __m256i, int const *, __m256i, 1)
 test_2 ( _mm_i64gather_epi32, __m128i, int const *, __m128i, 1)
 test_2 ( _mm256_i64gather_epi32, __m128i, int const *, __m256i, 1)
 
+/* rtmintrin.h */
+test_0 ( _xabort, void, 1)
+
 /* wmmintrin.h (AES/PCLMUL).  */
 #ifdef DIFFERENT_PRAGMAS
 #pragma GCC target ("aes,pclmul")
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 462f8c9..c160d71 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -180,7 +180,10 @@
 #define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1)
 #define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1)
 
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma")
+/* rtmintrin.h */
+#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
+
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm")
 #include <wmmintrin.h>
 #include <smmintrin.h>
 #include <mm3dnow.h>