From: Xishi Qiu Date: Fri, 30 Aug 2013 09:39:28 +0000 (+0800) Subject: doc: Documentation/DMA-attributes.txt fix typo X-Git-Tag: accepted/tizen/common/20141203.182822~318^2~68 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bf038227a01263dc29fa7053e600ec5a939d0bbd;p=platform%2Fkernel%2Flinux-arm64.git doc: Documentation/DMA-attributes.txt fix typo Fix some typos in Documentation/DMA-attributes.txt. Signed-off-by: Xishi Qiu Acked-by: Rob Landley Signed-off-by: Jiri Kosina --- diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index e59480d..cc2450d 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -13,7 +13,7 @@ all pending DMA writes to complete, and thus provides a mechanism to strictly order DMA from a device across all intervening busses and bridges. This barrier is not specific to a particular type of interconnect, it applies to the system as a whole, and so its -implementation must account for the idiosyncracies of the system all +implementation must account for the idiosyncrasies of the system all the way from the DMA device to memory. As an example of a situation where DMA_ATTR_WRITE_BARRIER would be @@ -60,7 +60,7 @@ such mapping is non-trivial task and consumes very limited resources Buffers allocated with this attribute can be only passed to user space by calling dma_mmap_attrs(). By using this API, you are guaranteeing that you won't dereference the pointer returned by dma_alloc_attr(). You -can threat it as a cookie that must be passed to dma_mmap_attrs() and +can treat it as a cookie that must be passed to dma_mmap_attrs() and dma_free_attrs(). Make sure that both of these also get this attribute set on each call. @@ -82,7 +82,7 @@ to 'device' domain, what synchronizes CPU caches for the given region (usually it means that the cache has been flushed or invalidated depending on the dma direction). However, next calls to dma_map_{single,page,sg}() for other devices will perform exactly the -same sychronization operation on the CPU cache. CPU cache sychronization +same synchronization operation on the CPU cache. CPU cache synchronization might be a time consuming operation, especially if the buffers are large, so it is highly recommended to avoid it if possible. DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of