From: Alex Richardson Date: Fri, 13 Dec 2019 11:28:20 +0000 (+0000) Subject: [NFC] Use EVT instead of bool for getSetCCInverse() X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=be15dfa88fb1ed94d12f374797f98ede6808f809;p=platform%2Fupstream%2Fllvm.git [NFC] Use EVT instead of bool for getSetCCInverse() Summary: The use of a boolean isInteger flag (generally initialized using VT.isInteger()) caused errors in our out-of-tree CHERI backend (https://github.com/CTSRD-CHERI/llvm-project). In our backend, pointers use a separate ValueType (iFATPTR) and therefore .isInteger() returns false. This meant that getSetCCInverse() was using the floating-point variant and generated incorrect code for us: `(void *)0x12033091e < (void *)0xffffffffffffffff` would return false. Committing this change will significantly reduce our merge conflicts for each upstream merge. Reviewers: spatel, bogner Reviewed By: bogner Subscribers: wuzish, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70917 --- diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index a9f601e..7650ca0 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -13,6 +13,8 @@ #ifndef LLVM_CODEGEN_ISDOPCODES_H #define LLVM_CODEGEN_ISDOPCODES_H +#include "llvm/CodeGen/ValueTypes.h" + namespace llvm { /// ISD namespace - This namespace contains an enum which represents all of the @@ -1082,7 +1084,7 @@ namespace ISD { /// Return the operation corresponding to !(X op Y), where 'op' is a valid /// SetCC operation. - CondCode getSetCCInverse(CondCode Operation, bool isInteger); + CondCode getSetCCInverse(CondCode Operation, EVT Type); /// Return the operation corresponding to (Y op X) when given the operation /// for (X op Y). @@ -1091,12 +1093,12 @@ namespace ISD { /// Return the result of a logical OR between different comparisons of /// identical values: ((X op1 Y) | (X op2 Y)). This function returns /// SETCC_INVALID if it is not possible to represent the resultant comparison. - CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); + CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type); /// Return the result of a logical AND between different comparisons of /// identical values: ((X op1 Y) & (X op2 Y)). This function returns /// SETCC_INVALID if it is not possible to represent the resultant comparison. - CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); + CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type); } // end llvm::ISD namespace diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c462a6b..15c2be1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4641,8 +4641,8 @@ SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) if (LL == RL && LR == RR) { - ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger) - : ISD::getSetCCOrOperation(CC0, CC1, IsInteger); + ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT) + : ISD::getSetCCOrOperation(CC0, CC1, OpVT); if (NewCC != ISD::SETCC_INVALID && (!LegalOperations || (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) && @@ -7047,7 +7047,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { SDValue LHS, RHS, CC; if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) { ISD::CondCode NotCC = ISD::getSetCCInverse(cast(CC)->get(), - LHS.getValueType().isInteger()); + LHS.getValueType()); if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { switch (N0Opcode) { @@ -20348,7 +20348,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) { if (Swap) { - CC = ISD::getSetCCInverse(CC, CmpOpVT.isInteger()); + CC = ISD::getSetCCInverse(CC, CmpOpVT); std::swap(N2C, N3C); } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 70966b6..7b3b1c0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1659,7 +1659,7 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode( } // Swapping operands didn't work. Try inverting the condition. bool NeedSwap = false; - InvCC = getSetCCInverse(CCCode, OpVT.isInteger()); + InvCC = getSetCCInverse(CCCode, OpVT); if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { // If inverting the condition is not enough, try swapping operands // on top of it. @@ -3614,8 +3614,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { // Try to legalize by inverting the condition. This is for targets that // might support an ordered version of a condition, but not the unordered // version (or vice versa). - ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, - Tmp1.getValueType().isInteger()); + ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType()); if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) { // Use the new condition code and swap true and false Legalized = true; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index a426e32..43938ab 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -356,9 +356,10 @@ ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { (OldG << 2)); // New L bit. } -ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { +ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) { + bool IsInteger = Type.isInteger(); unsigned Operation = Op; - if (isInteger) + if (IsInteger) Operation ^= 7; // Flip L, G, E bits, but not U. else Operation ^= 15; // Flip all of the condition bits. @@ -389,7 +390,8 @@ static int isSignedOp(ISD::CondCode Opcode) { } ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, - bool IsInteger) { + EVT Type) { + bool IsInteger = Type.isInteger(); if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) // Cannot fold a signed integer setcc with an unsigned integer setcc. return ISD::SETCC_INVALID; @@ -409,7 +411,8 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, } ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, - bool IsInteger) { + EVT Type) { + bool IsInteger = Type.isInteger(); if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) // Cannot fold a signed setcc with an unsigned setcc. return ISD::SETCC_INVALID; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f8afdaf..53f5c1c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -390,8 +390,10 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, NewRHS = DAG.getConstant(0, dl, RetVT); CCCode = getCmpLibcallCC(LC1); - if (ShouldInvertCC) - CCCode = getSetCCInverse(CCCode, /*isInteger=*/true); + if (ShouldInvertCC) { + assert(RetVT.isInteger()); + CCCode = getSetCCInverse(CCCode, RetVT); + } if (LC2 != RTLIB::UNKNOWN_LIBCALL) { SDValue Tmp = DAG.getNode( @@ -2812,7 +2814,8 @@ SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, // Note that where Y is variable and is known to have at most one bit set // (for example, if it is Z & 1) we cannot do this; the expressions are not // equivalent when Y == 0. - Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); + assert(OpVT.isInteger()); + Cond = ISD::getSetCCInverse(Cond, OpVT); if (DCI.isBeforeLegalizeOps() || isCondCodeLegal(Cond, N0.getSimpleValueType())) return DAG.getSetCC(DL, VT, N0, Zero, Cond); @@ -2901,7 +2904,8 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck( // What if we invert constants? (and the target predicate) I1.negate(); I01.negate(); - NewCond = getSetCCInverse(NewCond, /*isInteger=*/true); + assert(XVT.isInteger()); + NewCond = getSetCCInverse(NewCond, XVT); if (!checkConstants()) return SDValue(); // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256 @@ -3137,7 +3141,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0) SDValue Zero = DAG.getConstant(0, dl, CTVT); SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); - ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, true); + assert(CTVT.isInteger()); + ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT); SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne); SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond); @@ -3228,7 +3233,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode InvCond = ISD::getSetCCInverse( cast(TopSetCC.getOperand(2))->get(), - TopSetCC.getOperand(0).getValueType().isInteger()); + TopSetCC.getOperand(0).getValueType()); return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), TopSetCC.getOperand(1), InvCond); @@ -3392,8 +3397,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. ISD::CondCode CC = cast(N0.getOperand(2))->get(); - CC = ISD::getSetCCInverse(CC, - N0.getOperand(0).getValueType().isInteger()); + CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); if (DCI.isBeforeLegalizeOps() || isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index f601bf1..8350677 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1614,7 +1614,8 @@ static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, // All of the compare-mask comparisons are ordered, but we can switch // between the two by a double inversion. E.g. ULE == !OGT. Invert = true; - changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); + changeFPCCToAArch64CC(getSetCCInverse(CC, /* FP inverse */ MVT::f32), + CondCode, CondCode2); break; } } @@ -1861,7 +1862,7 @@ static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val, ISD::CondCode CC = cast(Val->getOperand(2))->get(); bool isInteger = LHS.getValueType().isInteger(); if (Negate) - CC = getSetCCInverse(CC, isInteger); + CC = getSetCCInverse(CC, LHS.getValueType()); SDLoc DL(Val); // Determine OutCC and handle FP special case. if (isInteger) { @@ -2333,7 +2334,7 @@ static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) { if (CTVal->isAllOnesValue() && CFVal->isNullValue()) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } // If the constants line up, perform the transform! @@ -5026,8 +5027,8 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (LHS.getValueType().isInteger()) { SDValue CCVal; - SDValue Cmp = - getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl); + SDValue Cmp = getAArch64Cmp( + LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl); // Note that we inverted the condition above, so we reverse the order of // the true and false operands here. This will allow the setcc to be @@ -5046,7 +5047,8 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { AArch64CC::CondCode CC1, CC2; changeFPCCToAArch64CC(CC, CC1, CC2); if (CC2 == AArch64CC::AL) { - changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2); + changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1, + CC2); SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32); // Note that we inverted the condition above, so we reverse the order of @@ -5107,18 +5109,18 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } else if (TVal.getOpcode() == ISD::XOR) { // If TVal is a NOT we want to swap TVal and FVal so that we can match // with a CSINV rather than a CSEL. if (isAllOnesConstant(TVal.getOperand(1))) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } } else if (TVal.getOpcode() == ISD::SUB) { // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so @@ -5126,7 +5128,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, if (isNullConstant(TVal.getOperand(0))) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } } else if (CTVal && CFVal) { const int64_t TrueVal = CTVal->getSExtValue(); @@ -5169,7 +5171,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, if (Swap) { std::swap(TVal, FVal); std::swap(CTVal, CFVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } if (Opcode != AArch64ISD::CSEL) { @@ -10430,10 +10432,10 @@ static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) { MVT::i32); Cmp = *InfoAndKind.Info.AArch64.Cmp; } else - Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0, - *InfoAndKind.Info.Generic.Opnd1, - ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true), - CCVal, DAG, dl); + Cmp = getAArch64Cmp( + *InfoAndKind.Info.Generic.Opnd0, *InfoAndKind.Info.Generic.Opnd1, + ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG, + dl); EVT VT = Op->getValueType(0); LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT)); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index e5b9424..b250087 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3568,8 +3568,8 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N, // select (setcc x, y), k, x -> select (setccinv x, y), x, k SDLoc SL(N); - ISD::CondCode NewCC = getSetCCInverse(cast(CC)->get(), - LHS.getValueType().isInteger()); + ISD::CondCode NewCC = + getSetCCInverse(cast(CC)->get(), LHS.getValueType()); SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC); return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 1f7f388..b02c460 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -974,8 +974,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const // Move hardware True/False values to the correct operand. if (isHWTrueValue(False) && isHWFalseValue(True)) { ISD::CondCode CCOpcode = cast(CC)->get(); - ISD::CondCode InverseCC = - ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); + ISD::CondCode InverseCC = ISD::getSetCCInverse(CCOpcode, CompareVT); if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) { std::swap(False, True); CC = DAG.getCondCode(InverseCC); @@ -1015,7 +1014,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const CC = DAG.getCondCode(CCSwapped); } else { // Try inverting the conditon and then swapping the operands - ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); + ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT); CCSwapped = ISD::getSetCCSwappedOperands(CCInv); if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) { std::swap(True, False); @@ -1041,7 +1040,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const case ISD::SETONE: case ISD::SETUNE: case ISD::SETNE: - CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); + CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT); Temp = True; True = False; False = Temp; @@ -1993,8 +1992,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, case ISD::SETNE: return LHS; case ISD::SETEQ: { ISD::CondCode LHSCC = cast(LHS.getOperand(4))->get(); - LHSCC = ISD::getSetCCInverse(LHSCC, - LHS.getOperand(0).getValueType().isInteger()); + LHSCC = ISD::getSetCCInverse(LHSCC, LHS.getOperand(0).getValueType()); if (DCI.isBeforeLegalizeOps() || isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType())) return DAG.getSelectCC(DL, diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e38ce70a..0151440 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4952,7 +4952,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { Opcode = ARMISD::CSINC; std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } if (Opcode) { @@ -4962,7 +4962,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) { std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } // Attempt to use ZR checking TVal is 0, possibly inverting the condition @@ -4971,7 +4971,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { if (FVal == 0 && Opcode != ARMISD::CSINC) { std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } if (TVal == 0) TrueVal = DAG.getRegister(ARM::ZR, MVT::i32); @@ -5015,7 +5015,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { ARMCC::CondCodes CondCode = IntCCToARMCC(CC); if (CondCode == ARMCC::LT || CondCode == ARMCC::LE || CondCode == ARMCC::VC || CondCode == ARMCC::NE) { - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); std::swap(TrueVal, FalseVal); } } @@ -14226,7 +14226,7 @@ static SDValue PerformHWLoopCombine(SDNode *N, return SDValue(); if (Negate) - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32); auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) { return (CC == ISD::SETEQ && Imm == 0) || diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 7d8f0e3..b9d881d 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -709,7 +709,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, SDValue True = N->getOperand(1); SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), - SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); + SetCC.getOperand(1), + ISD::getSetCCInverse(CC, SetCC.getValueType())); return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); } @@ -743,7 +744,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, if (Diff == -1) { ISD::CondCode CC = cast(SetCC.getOperand(2))->get(); SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), - SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); + SetCC.getOperand(1), + ISD::getSetCCInverse(CC, SetCC.getValueType())); return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index aac92ec..36d0d92 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -3597,7 +3597,7 @@ SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare, if (ConvOpts == SetccInGPROpts::ZExtInvert || ConvOpts == SetccInGPROpts::SExtInvert) - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, InputVT); bool Inputs32Bit = InputVT == MVT::i32; diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index fa21026..b655afe 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2693,7 +2693,7 @@ static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode, return Opcode; } - CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int); + CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int ? MVT::i32 : MVT::f32); if (unsigned Opcode = getVectorComparison(CC, Mode)) { Invert = true; return Opcode; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 866ee5b..2dcd2ee 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36887,9 +36887,8 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, if (TValIsAllZeros || FValIsAllOnes) { SDValue CC = Cond.getOperand(2); - ISD::CondCode NewCC = - ISD::getSetCCInverse(cast(CC)->get(), - Cond.getOperand(0).getValueType().isInteger()); + ISD::CondCode NewCC = ISD::getSetCCInverse( + cast(CC)->get(), Cond.getOperand(0).getValueType()); Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC); std::swap(LHS, RHS); @@ -37411,7 +37410,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, SDValue Other; if (ISD::isBuildVectorAllZeros(LHS.getNode())) { Other = RHS; - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, VT.getVectorElementType()); } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) { Other = LHS; } @@ -37483,7 +37482,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, SDValue Other; if (ISD::isBuildVectorAllOnes(LHS.getNode())) { Other = RHS; - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, VT.getVectorElementType()); } else if (ISD::isBuildVectorAllOnes(RHS.getNode())) { Other = LHS; }