From: Chris Forbes <chrisf@ijw.co.nz>
Date: Tue, 8 Oct 2013 09:09:28 +0000 (+1300)
Subject: i965: relax brw_texture_offset assert
X-Git-Tag: upstream/10.0.5~595
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bdcacaed9c64c49827d325d15ada2c482bfe1578;p=platform%2Fupstream%2Fmesa.git

i965: relax brw_texture_offset assert

Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 9f37013..7dabc47 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1596,7 +1596,7 @@ fs_visitor::visit(ir_texture *ir)
    }
 
    if (ir->offset != NULL && ir->op != ir_txf)
-      inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
+      inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
 
    if (ir->op == ir_tg4)
       inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 2fb43a6..df905fb 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -372,9 +372,14 @@ brw_math_function(enum opcode op)
 }
 
 uint32_t
-brw_texture_offset(ir_constant *offset)
+brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
 {
-   assert(offset != NULL);
+   /* If the driver does not support GL_ARB_gpu_shader5, the offset
+    * must be constant.
+    */
+   assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
+
+   if (!offset) return 0;  /* nonconstant offset; caller will handle it. */
 
    signed char offsets[3];
    for (unsigned i = 0; i < offset->type->vector_elements; i++)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 7cebf1f..cc76a44 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -77,7 +77,7 @@ public:
    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 };
 
-uint32_t brw_texture_offset(ir_constant *offset);
+uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
 
 #endif /* __cplusplus */
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c163c94..68d6cd9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2286,7 +2286,7 @@ vec4_visitor::visit(ir_texture *ir)
    inst->shadow_compare = ir->shadow_comparitor != NULL;
 
    if (use_texture_offset)
-      inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
+      inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
 
    /* Stuff the channel select bits in the top of the texture offset */
    if (ir->op == ir_tg4)