From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 7 Aug 2017 22:00:58 +0000 (+0000)
Subject: AMDGPU: Implement getMinimumNopSize
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bd57cea6e49e71f8224111ad8936ac4c1be5fbd5;p=platform%2Fupstream%2Fllvm.git

AMDGPU: Implement getMinimumNopSize

llvm-svn: 310310
---

diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index a50e3eb..1586914 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -43,6 +43,8 @@ public:
     llvm_unreachable("Not implemented");
   }
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
+
+  unsigned getMinimumNopSize() const override;
   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
@@ -133,6 +135,10 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
   return Infos[Kind - FirstTargetFixupKind];
 }
 
+unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
+  return 4;
+}
+
 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far