From: rsandifo Date: Fri, 12 Jan 2007 09:19:52 +0000 (+0000) Subject: gcc/ X-Git-Tag: upstream/4.9.2~51115 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bd40163f07d52977ff94189b9b80b1a2198491c1;p=platform%2Fupstream%2Flinaro-gcc.git gcc/ 200x-xx-xx Julian Brown Richard Sandiford * config/m68k/m68k.h (TARGET_CPU_CPP_BUILTINS): Use TUNE_68030 instead of TARGET_68030, TUNE_68040 instead of TARGET_68040, TUNE_68060 instead of TARGET_68060 and TUNE_CPU32 instead of TARGET_CPU32. (TARGET_CPU32): Rename to... (TUNE_CPU32): ...this. (TUNE_68000_10, TUNE_68030, TUNE_68040, TUNE_68060) (TUNE_CFV2): New macros. * config/m68k/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Simplify; remove conditions that are implied by TARGET_68020. * config/m68k/m68k.c (m68k_output_function_prologue): Use TUNE_68040 instead of TARGET_68040 and TUNE_CPU32 instead of TARGET_CPU32. (m68k_output_function_epilogue): Likewise. (m68k_rtx_costs): Likewise. Use TUNE_68060 instead of TARGET_68060 and TUNE_CFV2 instead of TARGET_5200. Use TUNE_68000_10 instead of "!TARGET_68020 && !TARGET_COLDFIRE" to choose between 68000 and non-68000 timings. Refactor multiplication and division costs. (output_addsi3): Use TUNE_68040 instead of TARGET_68040 and TUNE_CPU32 instead of TARGET_CPU32. (standard_68881_constant_p): Use TUNE_68040 instead of TARGET_68040 and TUNE_68060 instead of TARGET_68060. * config/m68k/m68k.md: Use TUNE_68040 instead of TARGET_68040, TUNE_68060 instead of TARGET_68060, and TUNE_CPU32 instead of TARGET_CPU32. (movsi_const0): Use TUNE_68000_10 rather than "!TARGET_68020 && !TARGET_COLDFIRE" to choose between moveq and clr. Likewise in the unnamed movsf pattern. (ashlsi_17_24, lshrsi_17_24): Guard with TUNE_68000_10 rather than "!TARGET_68020 && !TARGET_COLDFIRE". Likewise the unnamed ashiftrt pattern. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@120706 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f29bdf3..a8e0835 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,37 @@ +2007-01-12 Julian Brown + Richard Sandiford + + * config/m68k/m68k.h (TARGET_CPU_CPP_BUILTINS): Use TUNE_68030 + instead of TARGET_68030, TUNE_68040 instead of TARGET_68040, + TUNE_68060 instead of TARGET_68060 and TUNE_CPU32 instead of + TARGET_CPU32. + (TARGET_CPU32): Rename to... + (TUNE_CPU32): ...this. + (TUNE_68000_10, TUNE_68030, TUNE_68040, TUNE_68060) + (TUNE_CFV2): New macros. + * config/m68k/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Simplify; + remove conditions that are implied by TARGET_68020. + * config/m68k/m68k.c (m68k_output_function_prologue): Use TUNE_68040 + instead of TARGET_68040 and TUNE_CPU32 instead of TARGET_CPU32. + (m68k_output_function_epilogue): Likewise. + (m68k_rtx_costs): Likewise. Use TUNE_68060 instead of TARGET_68060 + and TUNE_CFV2 instead of TARGET_5200. Use TUNE_68000_10 instead of + "!TARGET_68020 && !TARGET_COLDFIRE" to choose between 68000 and + non-68000 timings. Refactor multiplication and division costs. + (output_addsi3): Use TUNE_68040 instead of TARGET_68040 and + TUNE_CPU32 instead of TARGET_CPU32. + (standard_68881_constant_p): Use TUNE_68040 instead of TARGET_68040 + and TUNE_68060 instead of TARGET_68060. + * config/m68k/m68k.md: Use TUNE_68040 instead of TARGET_68040, + TUNE_68060 instead of TARGET_68060, and TUNE_CPU32 instead of + TARGET_CPU32. + (movsi_const0): Use TUNE_68000_10 rather than "!TARGET_68020 + && !TARGET_COLDFIRE" to choose between moveq and clr. + Likewise in the unnamed movsf pattern. + (ashlsi_17_24, lshrsi_17_24): Guard with TUNE_68000_10 rather than + "!TARGET_68020 && !TARGET_COLDFIRE". Likewise the unnamed + ashiftrt pattern. + 2007-01-12 Richard Sandiford * config/m68k/m68k.h (TARGET_CPU_CPP_BUILTINS): Increase amount diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index af3a03f..0fae1d9 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -550,7 +550,7 @@ m68k_output_function_prologue (FILE *stream, if (frame_pointer_needed) { - if (current_frame.size == 0 && TARGET_68040) + if (current_frame.size == 0 && TUNE_68040) /* on the 68040, pea + move is faster than link.w 0 */ fprintf (stream, (MOTOROLA ? "\tpea (%s)\n\tmove.l %s,%s\n" @@ -584,14 +584,14 @@ m68k_output_function_prologue (FILE *stream, asm_fprintf (stream, "\tsubq" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); } - else if (fsize_with_regs <= 16 && TARGET_CPU32) + else if (fsize_with_regs <= 16 && TUNE_CPU32) /* On the CPU32 it is faster to use two subqw instructions to subtract a small integer (8 < N <= 16) to a register. */ asm_fprintf (stream, "\tsubq" ASM_DOT "w %I8,%Rsp\n" "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", fsize_with_regs - 8); - else if (TARGET_68040) + else if (TUNE_68040) /* Adding negative number is faster on the 68040. */ asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", -fsize_with_regs); @@ -1054,7 +1054,7 @@ m68k_output_function_epilogue (FILE *stream, asm_fprintf (stream, "\taddq" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); } - else if (fsize_with_regs <= 16 && TARGET_CPU32) + else if (fsize_with_regs <= 16 && TUNE_CPU32) { /* On the CPU32 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to a register. */ @@ -1065,7 +1065,7 @@ m68k_output_function_epilogue (FILE *stream, } else if (fsize_with_regs < 0x8000) { - if (TARGET_68040) + if (TUNE_68040) asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", fsize_with_regs); else @@ -1634,12 +1634,21 @@ m68k_rtx_costs (rtx x, int code, int outer_code, int *total) sometimes move insns are needed. */ /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ -#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 \ - : (TARGET_COLDFIRE && !TARGET_5200) ? 3 \ - : TARGET_COLDFIRE ? 10 : 13) -#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 \ - : (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5) -#define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12) +#define MULL_COST \ + (TUNE_68060 ? 2 \ + : TUNE_68040 ? 5 \ + : TUNE_CFV2 ? 10 \ + : TARGET_COLDFIRE ? 3 : 13) + +#define MULW_COST \ + (TUNE_68060 ? 2 \ + : TUNE_68040 ? 3 \ + : TUNE_68000_10 || TUNE_CFV2 ? 5 \ + : TARGET_COLDFIRE ? 2 : 8) + +#define DIVW_COST \ + (TARGET_CF_HWDIV ? 11 \ + : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) case PLUS: /* An lea costs about three times as much as a simple add. */ @@ -1661,12 +1670,12 @@ m68k_rtx_costs (rtx x, int code, int outer_code, int *total) case ASHIFT: case ASHIFTRT: case LSHIFTRT: - if (TARGET_68060) + if (TUNE_68060) { *total = COSTS_N_INSNS(1); return true; } - if (! TARGET_68020 && ! TARGET_COLDFIRE) + if (TUNE_68000_10) { if (GET_CODE (XEXP (x, 1)) == CONST_INT) { @@ -2560,7 +2569,7 @@ output_addsi3 (rtx *operands) /* On the CPU32 it is faster to use two addql instructions to add a small integer (8 < N <= 16) to a register. Likewise for subql. */ - if (TARGET_CPU32 && REG_P (operands[0])) + if (TUNE_CPU32 && REG_P (operands[0])) { if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16) @@ -2579,7 +2588,7 @@ output_addsi3 (rtx *operands) && INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) < 0x8000) { - if (TARGET_68040) + if (TUNE_68040) return "add%.w %2,%0"; else return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; @@ -2780,7 +2789,7 @@ standard_68881_constant_p (rtx x) /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be used at all on those chips. */ - if (TARGET_68040 || TARGET_68060) + if (TUNE_68040 || TUNE_68060) return 0; if (! inited_68881_table) diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 79533fa..b50bf10 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -42,31 +42,31 @@ Boston, MA 02110-1301, USA. */ builtin_define_std ("mc68000"); \ if (TARGET_68040_ONLY) \ { \ - if (TARGET_68060) \ + if (TUNE_68060) \ builtin_define_std ("mc68060"); \ else \ builtin_define_std ("mc68040"); \ } \ - else if (TARGET_68060) /* -m68020-60 */ \ + else if (TUNE_68060) /* -m68020-60 */ \ { \ builtin_define_std ("mc68060"); \ builtin_define_std ("mc68040"); \ builtin_define_std ("mc68030"); \ builtin_define_std ("mc68020"); \ } \ - else if (TARGET_68040) /* -m68020-40 */ \ + else if (TUNE_68040) /* -m68020-40 */ \ { \ builtin_define_std ("mc68040"); \ builtin_define_std ("mc68030"); \ builtin_define_std ("mc68020"); \ } \ - else if (TARGET_68030) \ + else if (TUNE_68030) \ builtin_define_std ("mc68030"); \ else if (TARGET_68020) \ builtin_define_std ("mc68020"); \ if (TARGET_68881) \ builtin_define ("__HAVE_68881__"); \ - if (TARGET_CPU32) \ + if (TUNE_CPU32) \ { \ builtin_define_std ("mc68332"); \ builtin_define_std ("mcpu32"); \ @@ -113,7 +113,7 @@ Boston, MA 02110-1301, USA. */ /* Compile for a CPU32. A 68020 without bitfields is a good heuristic for a CPU32. */ -#define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) +#define TUNE_CPU32 (TARGET_68020 && !TARGET_BITFIELD) /* Is the target a ColdFire? */ #define MASK_COLDFIRE \ @@ -126,6 +126,11 @@ Boston, MA 02110-1301, USA. */ /* Size (in bytes) of FPU registers. */ #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) +#define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE) +#define TUNE_68030 TARGET_68030 +#define TUNE_68040 TARGET_68040 +#define TUNE_68060 TARGET_68060 +#define TUNE_CFV2 TARGET_5200 #define OVERRIDE_OPTIONS override_options() diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index ef6cb04..92fd31c 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -82,7 +82,7 @@ ;;- be emulated in software by the OS. It is faster to avoid these ;;- instructions and issue a library call rather than trapping into ;;- the kernel. The affected instructions are fintrz and fscale. The -;;- TARGET_68040 flag turns the use of the opcodes off. +;;- TUNE_68040 flag turns the use of the opcodes off. ;;- The '040 also implements a set of new floating-point instructions ;;- which specify the rounding precision in the opcode. This finally @@ -104,7 +104,7 @@ ;;- instructions and issue a library call rather than trapping into ;;- the kernel. The affected instructions are: divs.l ,Dr:Dq; ;;- divu.l ,Dr:Dq; muls.l ,Dr:Dq; mulu.l ,Dr:Dq; and -;;- fscale. The TARGET_68060 flag turns the use of the opcodes off. +;;- fscale. The TUNE_68060 flag turns the use of the opcodes off. ;;- Some of these insn's are composites of several m68000 op codes. ;;- The assembler (or final @@??) insures that the appropriate one is @@ -618,13 +618,13 @@ if (ADDRESS_REG_P (operands[0])) { /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */ - if (!TARGET_68040 && !TARGET_68060) + if (!TUNE_68040 && !TUNE_68060) return "sub%.l %0,%0"; else return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE)) + if (DATA_REG_P (operands[0]) && TUNE_68000_10) return "moveq #0,%0"; return "clr%.l %0"; }) @@ -846,16 +846,14 @@ if (ADDRESS_REG_P (operands[0])) { /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */ - if (!TARGET_68040 && !TARGET_68060) + if (!TUNE_68040 && !TUNE_68060) return "sub%.l %0,%0"; else return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE)) - { - return "moveq #0,%0"; - } + if (DATA_REG_P (operands[0]) && TUNE_68000_10) + return "moveq #0,%0"; return "clr%.l %0"; } return "move%.l %1,%0"; @@ -1760,7 +1758,7 @@ (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] - "TARGET_68881 && TARGET_68040" + "TARGET_68881 && TUNE_68040" { CC_STATUS_INIT; return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!"; @@ -1771,7 +1769,7 @@ (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] - "TARGET_68881 && TARGET_68040" + "TARGET_68881 && TUNE_68040" { CC_STATUS_INIT; return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!"; @@ -1782,7 +1780,7 @@ (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] - "TARGET_68881 && TARGET_68040" + "TARGET_68881 && TUNE_68040" { CC_STATUS_INIT; return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!"; @@ -1794,13 +1792,13 @@ (define_expand "ftrunc2" [(set (match_operand:FP 0 "nonimmediate_operand" "") (fix:FP (match_operand:FP 1 "general_operand" "")))] - "TARGET_HARD_FLOAT && !TARGET_68040" + "TARGET_HARD_FLOAT && !TUNE_68040" "") (define_insn "ftrunc2_68881" [(set (match_operand:FP 0 "nonimmediate_operand" "=f") (fix:FP (match_operand:FP 1 "general_operand" "fm")))] - "TARGET_68881 && !TARGET_68040" + "TARGET_68881 && !TUNE_68040" { if (FP_REG_P (operands[1])) return "fintrz%.x %f1,%0"; @@ -2130,7 +2128,7 @@ /* On the CPU32 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to a register. Likewise for subqw. */ - if (TARGET_CPU32 && REG_P (operands[0])) + if (TUNE_CPU32 && REG_P (operands[0])) { if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16) @@ -2145,7 +2143,7 @@ return "subq%.w #8,%0\;subq%.w %2,%0"; } } - if (ADDRESS_REG_P (operands[0]) && !TARGET_68040) + if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; } return "add%.w %2,%0"; @@ -2185,7 +2183,7 @@ /* On the CPU32 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to a register. Likewise for subqw. */ - if (TARGET_CPU32 && REG_P (operands[0])) + if (TUNE_CPU32 && REG_P (operands[0])) { if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16) @@ -2200,7 +2198,7 @@ return "subq%.w #8,%0\;subq%.w %1,%0"; } } - if (ADDRESS_REG_P (operands[0]) && !TARGET_68040) + if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; } return "add%.w %1,%0"; @@ -2234,7 +2232,7 @@ /* On the CPU32 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to a register. Likewise for subqw. */ - if (TARGET_CPU32 && REG_P (operands[0])) + if (TUNE_CPU32 && REG_P (operands[0])) { if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16) @@ -2249,7 +2247,7 @@ return "subq%.w #8,%0\;subq%.w %1,%0"; } } - if (ADDRESS_REG_P (operands[0]) && !TARGET_68040) + if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; } return "add%.w %1,%0"; @@ -2670,7 +2668,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2681,7 +2679,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "mulu%.l %2,%3:%0") ; Match immediate case. For 2.4 only match things < 2^31. @@ -2696,7 +2694,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" "mulu%.l %2,%3:%0") @@ -2709,7 +2707,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2720,7 +2718,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_insn "" @@ -2731,7 +2729,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_expand "umulsi3_highpart" @@ -2743,7 +2741,7 @@ (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" { operands[3] = gen_reg_rtx (SImode); @@ -2767,7 +2765,7 @@ (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_insn "const_umulsi3_highpart" @@ -2778,7 +2776,7 @@ (match_operand:DI 3 "const_uint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_expand "smulsi3_highpart" @@ -2790,7 +2788,7 @@ (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" { operands[3] = gen_reg_rtx (SImode); if (GET_CODE (operands[2]) == CONST_INT) @@ -2810,7 +2808,7 @@ (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_insn "const_smulsi3_highpart" @@ -2821,7 +2819,7 @@ (match_operand:DI 3 "const_sint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" + "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_expand "mul3" @@ -2871,7 +2869,7 @@ "TARGET_68881" { if (GET_CODE (operands[2]) == CONST_DOUBLE - && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060) + && floating_exact_log2 (operands[2]) && !TUNE_68040 && !TUNE_68060) { int i = floating_exact_log2 (operands[2]); operands[2] = GEN_INT (i); @@ -4174,7 +4172,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (const_int 16)))] - "!TARGET_68060" + "!TUNE_68060" { CC_STATUS_INIT; return "swap %0\;clr%.w %0"; @@ -4189,8 +4187,9 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_COLDFIRE - && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "TUNE_68000_10 + && INTVAL (operands[2]) > 16 + && INTVAL (operands[2]) <= 24" { CC_STATUS_INIT; @@ -4246,7 +4245,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 16)))] - "!TARGET_68060" + "!TUNE_68060" "swap %0\;ext%.l %0") ;; On the 68000, this makes faster code in a special case. @@ -4255,8 +4254,9 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_COLDFIRE - && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "TUNE_68000_10 + && INTVAL (operands[2]) > 16 + && INTVAL (operands[2]) <= 24" { operands[2] = GEN_INT (INTVAL (operands[2]) - 16); return "swap %0\;asr%.w %2,%0\;ext%.l %0"; @@ -4548,7 +4548,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 16)))] - "!TARGET_68060" + "!TUNE_68060" { CC_STATUS_INIT; return "clr%.w %0\;swap %0"; @@ -4560,8 +4560,9 @@ [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_COLDFIRE - && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "TUNE_68000_10 + && INTVAL (operands[2]) > 16 + && INTVAL (operands[2]) <= 24" { /* I think lsr%.w sets the CC properly. */ operands[2] = GEN_INT (INTVAL (operands[2]) - 16); @@ -5201,7 +5202,7 @@ (eq:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5223,7 +5224,7 @@ (ne:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5245,7 +5246,7 @@ (gt:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5282,7 +5283,7 @@ (lt:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5319,7 +5320,7 @@ (ge:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5356,7 +5357,7 @@ (le:QI (cc0) (const_int 0)))] "" { - if ((TARGET_68060 || TARGET_COLDFIRE_FPU) + if ((TUNE_68060 || TARGET_COLDFIRE_FPU) && m68k_last_compare_had_fp_operands) { m68k_last_compare_had_fp_operands = 0; @@ -5391,7 +5392,7 @@ (define_expand "sordered" [(set (match_operand:QI 0 "register_operand" "") (ordered:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5400,7 +5401,7 @@ (define_insn "*sordered_1" [(set (match_operand:QI 0 "register_operand" "=d") (ordered:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsor %0"; @@ -5409,7 +5410,7 @@ (define_expand "sunordered" [(set (match_operand:QI 0 "register_operand" "") (unordered:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5418,7 +5419,7 @@ (define_insn "*sunordered_1" [(set (match_operand:QI 0 "register_operand" "=d") (unordered:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsun %0"; @@ -5427,7 +5428,7 @@ (define_expand "suneq" [(set (match_operand:QI 0 "register_operand" "") (uneq:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5436,7 +5437,7 @@ (define_insn "*suneq_1" [(set (match_operand:QI 0 "register_operand" "=d") (uneq:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsueq %0"; @@ -5445,7 +5446,7 @@ (define_expand "sunge" [(set (match_operand:QI 0 "register_operand" "") (unge:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5454,7 +5455,7 @@ (define_insn "*sunge_1" [(set (match_operand:QI 0 "register_operand" "=d") (unge:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsuge %0"; @@ -5463,7 +5464,7 @@ (define_expand "sungt" [(set (match_operand:QI 0 "register_operand" "") (ungt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5472,7 +5473,7 @@ (define_insn "*sungt_1" [(set (match_operand:QI 0 "register_operand" "=d") (ungt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsugt %0"; @@ -5481,7 +5482,7 @@ (define_expand "sunle" [(set (match_operand:QI 0 "register_operand" "") (unle:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5490,7 +5491,7 @@ (define_insn "*sunle_1" [(set (match_operand:QI 0 "register_operand" "=d") (unle:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsule %0"; @@ -5499,7 +5500,7 @@ (define_expand "sunlt" [(set (match_operand:QI 0 "register_operand" "") (unlt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5508,7 +5509,7 @@ (define_insn "*sunlt_1" [(set (match_operand:QI 0 "register_operand" "=d") (unlt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsult %0"; @@ -5517,7 +5518,7 @@ (define_expand "sltgt" [(set (match_operand:QI 0 "register_operand" "") (ltgt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { gcc_assert (m68k_last_compare_had_fp_operands); m68k_last_compare_had_fp_operands = 0; @@ -5526,7 +5527,7 @@ (define_insn "*sltgt_1" [(set (match_operand:QI 0 "register_operand" "=d") (ltgt:QI (cc0) (const_int 0)))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsogl %0"; @@ -5535,7 +5536,7 @@ (define_insn "*fsogt_1" [(set (match_operand:QI 0 "register_operand" "=d") (not:QI (unle:QI (cc0) (const_int 0))))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsogt %0"; @@ -5544,7 +5545,7 @@ (define_insn "*fsoge_1" [(set (match_operand:QI 0 "register_operand" "=d") (not:QI (unlt:QI (cc0) (const_int 0))))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsoge %0"; @@ -5553,7 +5554,7 @@ (define_insn "*fsolt_1" [(set (match_operand:QI 0 "register_operand" "=d") (not:QI (unge:QI (cc0) (const_int 0))))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsolt %0"; @@ -5562,7 +5563,7 @@ (define_insn "*fsole_1" [(set (match_operand:QI 0 "register_operand" "=d") (not:QI (ungt:QI (cc0) (const_int 0))))] - "TARGET_68881 && !TARGET_68060" + "TARGET_68881 && !TUNE_68060" { cc_status = cc_prev_status; return "fsole %0"; @@ -6625,14 +6626,14 @@ else output_asm_insn ("addq%.l %1,%0", xoperands); } - else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16) + else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16) { xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8); output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands); } else if (INTVAL (xoperands[1]) <= 0x7FFF) { - if (TARGET_68040) + if (TUNE_68040) output_asm_insn ("add%.w %1,%0", xoperands); else if (MOTOROLA) output_asm_insn ("lea (%c1,%0),%0", xoperands); @@ -6669,14 +6670,14 @@ else output_asm_insn ("addq%.l %1,%0", xoperands); } - else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16) + else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16) { xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8); output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands); } else if (INTVAL (xoperands[1]) <= 0x7FFF) { - if (TARGET_68040) + if (TUNE_68040) output_asm_insn ("add%.w %1,%0", xoperands); else if (MOTOROLA) output_asm_insn ("lea (%c1,%0),%0", xoperands); diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h index afec0bb..c2fb111 100644 --- a/gcc/config/m68k/netbsd-elf.h +++ b/gcc/config/m68k/netbsd-elf.h @@ -41,9 +41,7 @@ Boston, MA 02110-1301, USA. */ /* Don't try using XFmode on the 68010. */ #undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE \ - ((TARGET_68020 || TARGET_68040 || TARGET_68040_ONLY || \ - TARGET_68060) ? 80 : 64) +#define LONG_DOUBLE_TYPE_SIZE (TARGET_68020 ? 80 : 64) #ifdef __mc68010__ #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64