From: ktkachov Date: Tue, 9 Sep 2014 11:22:52 +0000 (+0000) Subject: [3/7] Convert FP mnemonics to UAL | mul+add patterns X-Git-Tag: upstream/5.3.0~5629 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bd23734550a2518b66f54a3bd69db6c982b6a590;p=platform%2Fupstream%2Flinaro-gcc.git [3/7] Convert FP mnemonics to UAL | mul+add patterns * config/arm/vfp.md (*mulsf3_vfp): Use UAL assembly syntax. (*muldf3_vfp): Likewise. (*mulsf3negsf_vfp): Likewise. (*muldf3negdf_vfp): Likewise. (*mulsf3addsf_vfp): Likewise. (*muldf3adddf_vfp): Likewise. (*mulsf3subsf_vfp): Likewise. (*muldf3subdf_vfp): Likewise. (*mulsf3negsfaddsf_vfp): Likewise. (*fmuldf3negdfadddf_vfp): Likewise. (*mulsf3negsfsubsf_vfp): Likewise. (*muldf3negdfsubdf_vfp): Likewise. * gcc.target/arm/vfp-1.c: Updated expected assembly. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215052 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a2c1d6..cbc9afd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,20 @@ 2014-09-09 Kyrylo Tkachov + * config/arm/vfp.md (*mulsf3_vfp): Use UAL assembly syntax. + (*muldf3_vfp): Likewise. + (*mulsf3negsf_vfp): Likewise. + (*muldf3negdf_vfp): Likewise. + (*mulsf3addsf_vfp): Likewise. + (*muldf3adddf_vfp): Likewise. + (*mulsf3subsf_vfp): Likewise. + (*muldf3subdf_vfp): Likewise. + (*mulsf3negsfaddsf_vfp): Likewise. + (*fmuldf3negdfadddf_vfp): Likewise. + (*mulsf3negsfsubsf_vfp): Likewise. + (*muldf3negdfsubdf_vfp): Likewise. + +2014-09-09 Kyrylo Tkachov + * config/arm/vfp.md (*abssf2_vfp): Use UAL assembly syntax. (*absdf2_vfp): Likewise. (*negsf2_vfp): Likewise. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 755229c..d165d7c 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -749,7 +749,7 @@ (mult:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fmuls%?\\t%0, %1, %2" + "vmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] @@ -760,7 +760,7 @@ (mult:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fmuld%?\\t%P0, %P1, %P2" + "vmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] @@ -771,7 +771,7 @@ (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fnmuls%?\\t%0, %1, %2" + "vnmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] @@ -782,7 +782,7 @@ (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fnmuld%?\\t%P0, %P1, %P2" + "vnmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] @@ -798,7 +798,7 @@ (match_operand:SF 3 "s_register_operand" "t")) (match_operand:SF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fmacs%?\\t%0, %2, %3" + "vmla%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] @@ -810,7 +810,7 @@ (match_operand:DF 3 "s_register_operand" "w")) (match_operand:DF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fmacd%?\\t%P0, %P2, %P3" + "vmla%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] @@ -823,7 +823,7 @@ (match_operand:SF 3 "s_register_operand" "t")) (match_operand:SF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fmscs%?\\t%0, %2, %3" + "vnmls%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] @@ -835,7 +835,7 @@ (match_operand:DF 3 "s_register_operand" "w")) (match_operand:DF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fmscd%?\\t%P0, %P2, %P3" + "vnmls%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] @@ -848,7 +848,7 @@ (mult:SF (match_operand:SF 2 "s_register_operand" "t") (match_operand:SF 3 "s_register_operand" "t"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fnmacs%?\\t%0, %2, %3" + "vmls%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] @@ -860,7 +860,7 @@ (mult:DF (match_operand:DF 2 "s_register_operand" "w") (match_operand:DF 3 "s_register_operand" "w"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fnmacd%?\\t%P0, %P2, %P3" + "vmls%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] @@ -875,7 +875,7 @@ (match_operand:SF 3 "s_register_operand" "t")) (match_operand:SF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fnmscs%?\\t%0, %2, %3" + "vnmla%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] @@ -888,7 +888,7 @@ (match_operand:DF 3 "s_register_operand" "w")) (match_operand:DF 1 "s_register_operand" "0")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fnmscd%?\\t%P0, %P2, %P3" + "vnmla%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a8fbe02..eb6b1f8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -4,6 +4,10 @@ 2014-09-09 Kyrylo Tkachov + * gcc.target/arm/vfp-1.c: Updated expected assembly. + +2014-09-09 Kyrylo Tkachov + * gcc.target/arm/pr51835.c: Update expected assembly. * gcc.target/arm/vfp-1.c: Likewise. * gcc.target/arm/vfp-ldmdbd.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc/testsuite/gcc.target/arm/vfp-1.c index 3027f10..43495ae 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/vfp-1.c @@ -26,22 +26,22 @@ void test_sf() { /* { dg-final { scan-assembler "vdiv.f32" } } */ f1 = f2 / f3; /* mulsf3_vfp */ - /* { dg-final { scan-assembler "fmuls" } } */ + /* { dg-final { scan-assembler "vmul.f32" } } */ f1 = f2 * f3; /* mulsf3negsf_vfp */ - /* { dg-final { scan-assembler "fnmuls" } } */ + /* { dg-final { scan-assembler "vnmul.f32" } } */ f1 = -f2 * f3; /* mulsf3addsf_vfp */ - /* { dg-final { scan-assembler "fmacs" } } */ + /* { dg-final { scan-assembler "vmla.f32" } } */ f1 = f2 * f3 + f1; /* mulsf3subsf_vfp */ - /* { dg-final { scan-assembler "fmscs" } } */ + /* { dg-final { scan-assembler "vnmls.f32" } } */ f1 = f2 * f3 - f1; /* mulsf3negsfaddsf_vfp */ - /* { dg-final { scan-assembler "fnmacs" } } */ + /* { dg-final { scan-assembler "vmls.f32" } } */ f1 = f2 - f3 * f1; /* mulsf3negsfsubsf_vfp */ - /* { dg-final { scan-assembler "fnmscs" } } */ + /* { dg-final { scan-assembler "vnmla.f32" } } */ f1 = -f2 * f3 - f1; /* sqrtsf2_vfp */ /* { dg-final { scan-assembler "fsqrts" } } */ @@ -67,22 +67,22 @@ void test_df() { /* { dg-final { scan-assembler "vdiv.f64" } } */ d1 = d2 / d3; /* muldf3_vfp */ - /* { dg-final { scan-assembler "fmuld" } } */ + /* { dg-final { scan-assembler "vmul.f64" } } */ d1 = d2 * d3; /* muldf3negdf_vfp */ - /* { dg-final { scan-assembler "fnmuld" } } */ + /* { dg-final { scan-assembler "vnmul.f64" } } */ d1 = -d2 * d3; /* muldf3adddf_vfp */ - /* { dg-final { scan-assembler "fmacd" } } */ + /* { dg-final { scan-assembler "vmla.f64" } } */ d1 = d2 * d3 + d1; /* muldf3subdf_vfp */ - /* { dg-final { scan-assembler "fmscd" } } */ + /* { dg-final { scan-assembler "vnmls.f64" } } */ d1 = d2 * d3 - d1; /* muldf3negdfadddf_vfp */ - /* { dg-final { scan-assembler "fnmacd" } } */ + /* { dg-final { scan-assembler "vmls.f64" } } */ d1 = d2 - d3 * d1; /* muldf3negdfsubdf_vfp */ - /* { dg-final { scan-assembler "fnmscd" } } */ + /* { dg-final { scan-assembler "vnmla.f64" } } */ d1 = -d2 * d3 - d1; /* sqrtdf2_vfp */ /* { dg-final { scan-assembler "fsqrtd" } } */