From: Hal Feng Date: Mon, 31 Oct 2022 05:52:18 +0000 (+0800) Subject: clk: starfive: Keep the clock apb0 enabled always X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bcf29ef5cbd1b59173ef1fd2a667b6088a44c522;p=platform%2Fkernel%2Flinux-starfive.git clk: starfive: Keep the clock apb0 enabled always This solves crush problem of i2c runtime pm and prevents some aon modules from working abnormally. Signed-off-by: Hal Feng --- diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index 2b02740..7b52a61 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -50,7 +50,7 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = { JH7110_GATE(JH7110_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_STG_AXIAHB), JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func", 8, JH7110_STG_AXIAHB), - JH7110_GATE(JH7110_APB0, "apb0", CLK_IGNORE_UNUSED, JH7110_APB_BUS), + JH7110_GATE(JH7110_APB0, "apb0", CLK_IS_CRITICAL, JH7110_APB_BUS), JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT), JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT), JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),