From: Sanjay Patel <spatel@rotateright.com>
Date: Thu, 5 Jul 2018 13:16:46 +0000 (+0000)
Subject: [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC
X-Git-Tag: llvmorg-7.0.0-rc1~2159
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bce899ff599e219d757e40662e11bcebd4cf4f42;p=platform%2Fupstream%2Fllvm.git

[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC

llvm-svn: 336348
---

diff --git a/llvm/test/CodeGen/AArch64/signbit-shift.ll b/llvm/test/CodeGen/AArch64/signbit-shift.ll
new file mode 100644
index 0000000..f9300ad
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/signbit-shift.ll
@@ -0,0 +1,148 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+; If positive...
+
+define i32 @zext_ifpos(i32 %x) {
+; CHECK-LABEL: zext_ifpos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    eor w0, w8, #0x1
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_zext_ifpos(i32 %x) {
+; CHECK-LABEL: add_zext_ifpos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    eor w8, w8, #0x1
+; CHECK-NEXT:    add w0, w8, #41 // =41
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_tval_bigger:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    mov w8, #41
+; CHECK-NEXT:    cinc w0, w8, ge
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifpos(i32 %x) {
+; CHECK-LABEL: sext_ifpos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-1
+; CHECK-NEXT:    eor w0, w8, w0, asr #31
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_sext_ifpos(i32 %x) {
+; CHECK-LABEL: add_sext_ifpos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    eor w8, w8, #0x1
+; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    sub w0, w9, w8
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_fval_bigger:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    mov w8, #41
+; CHECK-NEXT:    cinc w0, w8, lt
+; CHECK-NEXT:    ret
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
+; If negative...
+
+define i32 @zext_ifneg(i32 %x) {
+; CHECK-LABEL: zext_ifneg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w0, w0, #31
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %r = zext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_zext_ifneg(i32 %x) {
+; CHECK-LABEL: add_zext_ifneg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    add w0, w8, #41 // =41
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_tval_bigger:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    mov w8, #41
+; CHECK-NEXT:    cinc w0, w8, lt
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifneg(i32 %x) {
+; CHECK-LABEL: sext_ifneg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr w0, w0, #31
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %r = sext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_sext_ifneg(i32 %x) {
+; CHECK-LABEL: add_sext_ifneg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #42
+; CHECK-NEXT:    sub w0, w8, w0, lsr #31
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_fval_bigger:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    mov w8, #41
+; CHECK-NEXT:    cinc w0, w8, ge
+; CHECK-NEXT:    ret
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
new file mode 100644
index 0000000..a64e71b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
+
+; If positive...
+
+define i32 @zext_ifpos(i32 %x) {
+; CHECK-LABEL: zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_zext_ifpos(i32 %x) {
+; CHECK-LABEL: add_zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    addi 3, 3, 41
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 41
+; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifpos(i32 %x) {
+; CHECK-LABEL: sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_sext_ifpos(i32 %x) {
+; CHECK-LABEL: add_sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    addi 3, 3, 42
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 42
+; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    li 3, 41
+; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
+; If negative...
+
+define i32 @zext_ifneg(i32 %x) {
+; CHECK-LABEL: zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = zext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_zext_ifneg(i32 %x) {
+; CHECK-LABEL: add_zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    addi 3, 3, 41
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 41
+; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifneg(i32 %x) {
+; CHECK-LABEL: sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = sext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_sext_ifneg(i32 %x) {
+; CHECK-LABEL: add_sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    addi 3, 3, 42
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 42
+; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    li 3, 41
+; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
diff --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll
new file mode 100644
index 0000000..d974187
--- /dev/null
+++ b/llvm/test/CodeGen/X86/signbit-shift.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+; If positive...
+
+define i32 @zext_ifpos(i32 %x) {
+; CHECK-LABEL: zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_zext_ifpos(i32 %x) {
+; CHECK-LABEL: add_zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    addl $41, %eax
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    addl $41, %eax
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifpos(i32 %x) {
+; CHECK-LABEL: sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_sext_ifpos(i32 %x) {
+; CHECK-LABEL: add_sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %cl
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setns %cl
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
+; If negative...
+
+define i32 @zext_ifneg(i32 %x) {
+; CHECK-LABEL: zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %r = zext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_zext_ifneg(i32 %x) {
+; CHECK-LABEL: add_zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    leal 41(%rdi), %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    leal 41(%rdi), %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifneg(i32 %x) {
+; CHECK-LABEL: sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sarl $31, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %r = sext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_sext_ifneg(i32 %x) {
+; CHECK-LABEL: add_sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    retq
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+