From: Francisco Jerez Date: Thu, 12 Jan 2017 03:55:33 +0000 (-0800) Subject: intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32. X-Git-Tag: upstream/19.0.0~4182 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bcbc7d3a1756af9f3135f53c89be253732c9e39c;p=platform%2Fupstream%2Fmesa.git intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32. Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index b881975..1e84274 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -185,11 +185,15 @@ emit_system_values_block(nir_block *block, fs_visitor *v) * masks for 2 and 3) in SIMD16. */ fs_reg shifted = abld.vgrf(BRW_REGISTER_TYPE_UW, 1); - abld.SHR(shifted, - stride(byte_offset(retype(brw_vec1_grf(1, 0), - BRW_REGISTER_TYPE_UB), 28), - 1, 8, 0), - brw_imm_v(0x76543210)); + + for (unsigned i = 0; i < DIV_ROUND_UP(v->dispatch_width, 16); i++) { + const fs_builder hbld = abld.group(MIN2(16, v->dispatch_width), i); + hbld.SHR(offset(shifted, hbld, i), + stride(retype(brw_vec1_grf(1 + i, 7), + BRW_REGISTER_TYPE_UB), + 1, 8, 0), + brw_imm_v(0x76543210)); + } /* A set bit in the pixel mask means the channel is enabled, but * that is the opposite of gl_HelperInvocation so we need to invert