From: Russell King (Oracle) Date: Wed, 18 May 2022 14:54:42 +0000 (+0100) Subject: net: mtk_eth_soc: add mask and update PCS speed definitions X-Git-Tag: v6.1-rc5~1274^2~54^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bc5e93e0cd22e360eda23859b939280205567580;p=platform%2Fkernel%2Flinux-starfive.git net: mtk_eth_soc: add mask and update PCS speed definitions The PCS speed setting is a two bit field, but it is defined as two separate bits. Add a bitfield mask for the speed definitions, an use the FIELD_PREP() macro to define each PCS speed. Signed-off-by: Russell King (Oracle) Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 085f53d..4f97195 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -17,6 +17,7 @@ #include #include #include +#include #include "mtk_ppe.h" #define MTK_QDMA_PAGE_SIZE 2048 @@ -493,9 +494,10 @@ #define SGMSYS_SGMII_MODE 0x20 #define SGMII_IF_MODE_BIT0 BIT(0) #define SGMII_SPEED_DUPLEX_AN BIT(1) -#define SGMII_SPEED_10 0x0 -#define SGMII_SPEED_100 BIT(2) -#define SGMII_SPEED_1000 BIT(3) +#define SGMII_SPEED_MASK GENMASK(3, 2) +#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) +#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) +#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) #define SGMII_DUPLEX_FULL BIT(4) #define SGMII_IF_MODE_BIT5 BIT(5) #define SGMII_REMOTE_FAULT_DIS BIT(8)