From: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Date: Mon, 1 Jul 2019 06:49:25 +0000 (+0530)
Subject: net: zynq_gem: Remove check for Versal
X-Git-Tag: v2020.10~561^2~61
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bc493d911e8c4e59ddaf0def0d35f1e2db0899ab;p=platform%2Fkernel%2Fu-boot.git

net: zynq_gem: Remove check for Versal

This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a35ecab..a7a6ce9 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
 		break;
 	}
 
-#if !defined(CONFIG_ARCH_VERSAL)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
 	}
-#else
-	debug("requested clk_rate %ld\n", clk_rate);
-#endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);