From: Baptiste Saleil <baptiste.saleil@ibm.com>
Date: Mon, 21 Sep 2020 21:03:34 +0000 (-0500)
Subject: [PowerPC] Remove unnecessary patterns and types
X-Git-Tag: llvmorg-13-init~11387
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bb821355387fb4320322b8c2ff63994fffaf49ce;p=platform%2Fupstream%2Fllvm.git

[PowerPC] Remove unnecessary patterns and types

These patterns and type uses were added by mistake by commit
1372e23c7d4b25fd23689842246e66f70c949b46
---

diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 00fd756..351f08d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -747,7 +747,7 @@ let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
                                   IIC_LdStLFD, []>;
   def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
                               "lxvpx $XTp, $src", IIC_LdStLFD,
-                              [(set v4i64:$XTp, (load xaddr:$src))]>;
+                              []>;
   let Predicates = [PrefixInstrs] in {
     defm PLXVP :
       8LS_DForm_R_XTp5_SI34_MEM_p<1, 58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
@@ -762,7 +762,7 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
                                    IIC_LdStLFD, []>;
   def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
                                "stxvpx $XTp, $dst", IIC_LdStLFD,
-                               [(store v4i64:$XTp, xaddr:$dst)]>;
+                               []>;
   let Predicates = [PrefixInstrs] in {
     defm PSTXVP :
       8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 3a5df25..850d7c6 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -399,7 +399,7 @@ def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
 
 // Allocate in the same order as the underlying VSX registers.
 def VSRpRC :
-  RegisterClass<"PPC", [v4i64,v4f64,v8i32,v8f32,v16i16,v32i8,v256i1], 128,
+  RegisterClass<"PPC", [v256i1], 128,
                 (add (sequence "VSRp%u", 0, 6),
                      (sequence "VSRp%u", 15, 7), VSRp17, VSRp18,
                      VSRp16, VSRp19, VSRp20, VSRp21, VSRp22, VSRp23,