From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Thu, 24 Oct 2013 17:03:44 +0000 (+0200)
Subject: microblaze: Improve srl
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~1277
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bb3cb951ef530da7d248051347c974e4d20e6ea0;p=sdk%2Femulator%2Fqemu.git

microblaze: Improve srl

write_carry only looks at bit zero, no need to mask out the others.

Meassured a 12% speed improvement in linux-user srl loops.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 916db15..93aafac 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -780,13 +780,10 @@ static void dec_bit(DisasContext *dc)
         case 0x1:
         case 0x41:
             /* srl.  */
-            t0 = tcg_temp_new();
             LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
 
-            /* Update carry.  */
-            tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
-            write_carry(dc, t0);
-            tcg_temp_free(t0);
+            /* Update carry. Note that write carry only looks at the LSB.  */
+            write_carry(dc, cpu_R[dc->ra]);
             if (dc->rd) {
                 if (op == 0x41)
                     tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);