From: Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Date: Fri, 6 Jul 2018 13:46:10 +0000 (+0000)
Subject: [llvm-mca] A write latency cannot be a negative value. NFC
X-Git-Tag: llvmorg-7.0.0-rc1~2073
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=bb25e27f58482308be014da8fbcdcb8630a817bd;p=platform%2Fupstream%2Fllvm.git

[llvm-mca] A write latency cannot be a negative value. NFC

llvm-svn: 336437
---

diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index b1ed2da..5b6b31b 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -196,7 +196,8 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
       const MCWriteLatencyEntry &WLE =
           *STI.getWriteLatencyEntry(&SCDesc, CurrentDef);
       // Conservatively default to MaxLatency.
-      Write.Latency = WLE.Cycles == -1 ? ID.MaxLatency : WLE.Cycles;
+      Write.Latency = WLE.Cycles < 0 ? ID.MaxLatency
+                                     : static_cast<unsigned>(WLE.Cycles);
       Write.SClassOrWriteResourceID = WLE.WriteResourceID;
     } else {
       // Assign a default latency for this write.
@@ -225,7 +226,8 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
       const MCWriteLatencyEntry &WLE =
           *STI.getWriteLatencyEntry(&SCDesc, Index);
       // Conservatively default to MaxLatency.
-      Write.Latency = WLE.Cycles == -1 ? ID.MaxLatency : WLE.Cycles;
+      Write.Latency = WLE.Cycles < 0 ? ID.MaxLatency
+                                     : static_cast<unsigned>(WLE.Cycles);
       Write.SClassOrWriteResourceID = WLE.WriteResourceID;
     } else {
       // Assign a default latency for this write.
diff --git a/llvm/tools/llvm-mca/Instruction.cpp b/llvm/tools/llvm-mca/Instruction.cpp
index dbf2d5f..53f0d67 100644
--- a/llvm/tools/llvm-mca/Instruction.cpp
+++ b/llvm/tools/llvm-mca/Instruction.cpp
@@ -41,7 +41,7 @@ void ReadState::writeStartEvent(unsigned Cycles) {
 void WriteState::onInstructionIssued() {
   assert(CyclesLeft == UNKNOWN_CYCLES);
   // Update the number of cycles left based on the WriteDescriptor info.
-  CyclesLeft = WD.Latency;
+  CyclesLeft = getLatency();
 
   // Now that the time left before write-back is known, notify
   // all the users.
@@ -93,7 +93,7 @@ void ReadState::cycleEvent() {
 
 #ifndef NDEBUG
 void WriteState::dump() const {
-  dbgs() << "{ OpIdx=" << WD.OpIndex << ", Lat=" << WD.Latency << ", RegID "
+  dbgs() << "{ OpIdx=" << WD.OpIndex << ", Lat=" << getLatency() << ", RegID "
          << getRegisterID() << ", Cycles Left=" << getCyclesLeft() << " }";
 }
 
diff --git a/llvm/tools/llvm-mca/Instruction.h b/llvm/tools/llvm-mca/Instruction.h
index c2d1761..3588fb0b 100644
--- a/llvm/tools/llvm-mca/Instruction.h
+++ b/llvm/tools/llvm-mca/Instruction.h
@@ -28,11 +28,6 @@
 
 namespace mca {
 
-struct WriteDescriptor;
-struct ReadDescriptor;
-class WriteState;
-class ReadState;
-
 constexpr int UNKNOWN_CYCLES = -512;
 
 /// A register write descriptor.
@@ -42,7 +37,7 @@ struct WriteDescriptor {
   // a bitwise not of the OpIndex.
   int OpIndex;
   // Write latency. Number of cycles before write-back stage.
-  int Latency;
+  unsigned Latency;
   // This field is set to a value different than zero only if this
   // is an implicit definition.
   unsigned RegisterID;
@@ -81,6 +76,8 @@ struct ReadDescriptor {
   bool isImplicitRead() const { return OpIndex < 0; };
 };
 
+class ReadState;
+
 /// Tracks uses of a register definition (e.g. register write).
 ///
 /// Each implicit/explicit register write is associated with an instance of
@@ -123,6 +120,7 @@ public:
   int getCyclesLeft() const { return CyclesLeft; }
   unsigned getWriteResourceID() const { return WD.SClassOrWriteResourceID; }
   unsigned getRegisterID() const { return RegisterID; }
+  unsigned getLatency() const { return WD.Latency; }
 
   void addUser(ReadState *Use, int ReadAdvance);
   unsigned getNumUsers() const { return Users.size(); }