From: Yao Qi <yao.qi@linaro.org>
Date: Mon, 4 Sep 2017 10:33:56 +0000 (+0100)
Subject: Let i386_target_description return tdesc_i386_mmx
X-Git-Tag: users/ARM/embedded-binutils-master-2017q4~1209
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=badc00202024619e1c868b8cf70fe6351fc028c3;p=platform%2Fupstream%2Fbinutils.git

Let i386_target_description return tdesc_i386_mmx

This patch remove the usage of tdesc_i386_mmx in i386-go32-tdep.c, and use
i386_target_description to get it instead.

gdb:

2017-09-04  Yao Qi  <yao.qi@linaro.org>

	* i386-go32-tdep.c: Include x86-xstate.h.
	(i386_go32_init_abi): Call i386_target_description.
	* i386-tdep.c (i386_target_description): Return tdesc_i386_mmx
	if xcr0 is X86_XSTATE_X87_MASK.
	* i386-tdep.h (tdesc_i386): Remove the declaration.
	(tdesc_i386_mmx): Likewise.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index e965e26..3068050 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,5 +1,14 @@
 2017-09-04  Yao Qi  <yao.qi@linaro.org>
 
+	* i386-go32-tdep.c: Include x86-xstate.h.
+	(i386_go32_init_abi): Call i386_target_description.
+	* i386-tdep.c (i386_target_description): Return tdesc_i386_mmx
+	if xcr0 is X86_XSTATE_X87_MASK.
+	* i386-tdep.h (tdesc_i386): Remove the declaration.
+	(tdesc_i386_mmx): Likewise.
+
+2017-09-04  Yao Qi  <yao.qi@linaro.org>
+
 	* i386-fbsd-tdep.c (i386fbsd_core_read_xcr0): Return
 	X86_XSTATE_SSE_MASK instead of 0.
 
diff --git a/gdb/i386-go32-tdep.c b/gdb/i386-go32-tdep.c
index 5bd4857..6778e52 100644
--- a/gdb/i386-go32-tdep.c
+++ b/gdb/i386-go32-tdep.c
@@ -19,6 +19,7 @@
 
 #include "defs.h"
 #include "i386-tdep.h"
+#include "x86-xstate.h"
 #include "target-descriptions.h"
 #include "osabi.h"
 
@@ -34,7 +35,7 @@ i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 
   /* DJGPP does not support the SSE registers.  */
   if (!tdesc_has_registers (info.target_desc))
-    tdep->tdesc = tdesc_i386_mmx;
+    tdep->tdesc = i386_target_description (X86_XSTATE_X87_MASK);
 
   /* Native compiler is GCC, which uses the SVR4 register numbering
      even in COFF and STABS.  See the comment in i386_gdbarch_init,
diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c
index 9d0dd3d..d162e92 100644
--- a/gdb/i386-tdep.c
+++ b/gdb/i386-tdep.c
@@ -8730,6 +8730,10 @@ i386_target_description (uint64_t xcr0)
       return tdesc_i386_mpx;
     case X86_XSTATE_AVX_MASK:
       return tdesc_i386_avx;
+    case X86_XSTATE_SSE_MASK:
+      return tdesc_i386;
+    case X86_XSTATE_X87_MASK:
+      return tdesc_i386_mmx;
     default:
       return tdesc_i386;
     }
diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h
index 1ce89fc..99b89e7 100644
--- a/gdb/i386-tdep.h
+++ b/gdb/i386-tdep.h
@@ -339,9 +339,6 @@ enum record_i386_regnum
 /* Size of the largest register.  */
 #define I386_MAX_REGISTER_SIZE	64
 
-extern struct target_desc *tdesc_i386;
-extern struct target_desc *tdesc_i386_mmx;
-
 /* Types for i386-specific registers.  */
 extern struct type *i387_ext_type (struct gdbarch *gdbarch);