From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Date: Wed, 10 Jul 2019 11:29:24 +0000 (+0530)
Subject: arm64: dts: sdm845: Add device node for Last level cache controller
X-Git-Tag: v5.4-rc1~184^2~6^2~28
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ba0411ddd133b34fd715f17b9c0c29027bfa92a8;p=platform%2Fkernel%2Flinux-rpi.git

arm64: dts: sdm845: Add device node for Last level cache controller

Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c8ebe21..40ec823 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1275,6 +1275,13 @@
 			};
 		};
 
+		cache-controller@1100000 {
+			compatible = "qcom,sdm845-llcc";
+			reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
+			reg-names = "llcc_base", "llcc_broadcast_base";
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";