From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: Mon, 1 Oct 2018 14:13:56 +0000 (+0200)
Subject: arm64: dts: marvell: add AP806 SEI subnode
X-Git-Tag: v5.15~7693^2~5^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b9a5950fc52763401fc774dfb0fccc02f0c9baf5;p=platform%2Fkernel%2Flinux-starfive.git

arm64: dts: marvell: add AP806 SEI subnode

Add the System Error Interrupt node, representing an IRQ chip which is
part of the GIC. The SEI node aggregates interrupts from the AP through
wired interrupts, and from the CPs through MSIs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 3032f04..073610a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -152,6 +152,15 @@
 				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			sei: interrupt-controller@3f0200 {
+				compatible = "marvell,ap806-sei";
+				reg = <0x3f0200 0x40>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				msi-controller;
+			};
+
 			xor@400000 {
 				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 				reg = <0x400000 0x1000>,