From: Zenghui Yu Date: Wed, 4 Mar 2020 20:33:11 +0000 (+0000) Subject: irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation X-Git-Tag: v5.10.7~2879^2^2~2^2~12 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b978c25f6ee7d4c79cbe918eed684e53887ec001;p=platform%2Fkernel%2Flinux-rpi.git irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation In GICv4.1, we emulate a guest-issued INVALL command by a direct write to GICR_INVALLR. Before we finish the emulation and go back to guest, let's make sure the physical invalidate operation is actually completed and no stale data will be left in redistributor. Per the specification, this can be achieved by polling the GICR_SYNCR.Busy bit (to zero). Signed-off-by: Zenghui Yu Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Link: https://lore.kernel.org/r/20200302092145.899-1-yuzenghui@huawei.com Link: https://lore.kernel.org/r/20200304203330.4967-5-maz@kernel.org --- diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 1af7139..c843702 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3827,6 +3827,8 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe) /* Target the redistributor this vPE is currently known on */ rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; gic_write_lpir(val, rdbase + GICR_INVALLR); + + wait_for_syncr(rdbase); } static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)