From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed, 1 Mar 2017 00:09:58 +0000 (-0800)
Subject: i965: Move a couple of #defines from brw_context to brw_compiler
X-Git-Tag: upstream/17.1.0~1838
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b97782c364cfc15a8136032805975fd72266d14c;p=platform%2Fupstream%2Fmesa.git

i965: Move a couple of #defines from brw_context to brw_compiler

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
index 3b3b7e0..297d8f8 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -492,6 +492,22 @@ typedef enum
 } brw_varying_slot;
 
 /**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry.  This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
+    ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
+
+/**
  * Data structure recording the relationship between the gl_varying_slot enum
  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
  * single octaword within the VUE (128 bits).
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 7ff7b74..c9a931c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -328,15 +328,6 @@ struct brw_program {
 };
 
 
-/**
- * Bitmask indicating which fragment shader inputs represent varyings (and
- * hence have to be delivered to the fragment shader by the SF/SBE stage).
- */
-#define BRW_FS_VARYING_INPUT_MASK \
-   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
-    ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
-
-
 struct brw_sf_prog_data {
    GLuint urb_read_length;
    GLuint total_grf;
@@ -351,15 +342,6 @@ struct brw_sf_prog_data {
 };
 
 
-/**
- * We always program SF to start reading at an offset of 1 (2 varying slots)
- * from the start of the vertex URB entry.  This causes it to skip:
- * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
- * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
- */
-#define BRW_SF_URB_ENTRY_READ_OFFSET 1
-
-
 struct brw_clip_prog_data {
    GLuint curb_read_length;	/* user planes? */
    GLuint clip_mode;