From: Xingyu Wu <xingyu.wu@starfivetech.com>
Date: Mon, 6 Mar 2023 02:42:07 +0000 (+0800)
Subject: riscv: dts: starfive: jh7100: Add watchdog node
X-Git-Tag: accepted/tizen/unified/riscv/20230718.024919~194
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b965f2d91ced9657386a3a40f96556e1cceadbf3;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: jh7100: Add watchdog node

Add watchdog node for the StarFive JH7100 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 0004474..4218621 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -238,5 +238,15 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+
+		watchdog@12480000 {
+			compatible = "starfive,jh7100-wdt";
+			reg = <0x0 0x12480000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
+				 <&clkgen JH7100_CLK_WDT_CORE>;
+			clock-names = "apb", "core";
+			resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
+				 <&rstgen JH7100_RSTN_WDT>;
+		};
 	};
 };