From: Jakub Jelinek Date: Thu, 2 Jun 2016 09:43:52 +0000 (+0200) Subject: sse.md (*vec_concatv2di): Add x86_avx512dq v=Yv,rm alternative. X-Git-Tag: upstream/12.2.0~46675 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b93b1475cdfb3ea6723fd1314c0d7e4482bcb3b6;p=platform%2Fupstream%2Fgcc.git sse.md (*vec_concatv2di): Add x86_avx512dq v=Yv,rm alternative. * config/i386/sse.md (*vec_concatv2di): Add x86_avx512dq v=Yv,rm alternative. Change x=xm,C alternative to v=vm,C, x=x,x alternative to v=Yv,Yv and x=x,m to v=v,m. Use maybe_evex prefix attribute instead of vex for the last two above mentioned alternatives. * gcc.target/i386/avx512dq-concatv2di-1.c: New test. * gcc.target/i386/avx512vl-concatv2di-1.c: New test. * gcc.target/i386/sse2-init-v2di-2.c: Adjust expected vec_concatv2di alternative number. From-SVN: r237028 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 23171c5..ed73991 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-06-02 Jakub Jelinek + + * config/i386/sse.md (*vec_concatv2di): Add x86_avx512dq v=Yv,rm + alternative. Change x=xm,C alternative to v=vm,C, x=x,x alternative + to v=Yv,Yv and x=x,m to v=v,m. Use maybe_evex prefix attribute + instead of vex for the last two above mentioned alternatives. + 2016-06-02 Kyrylo Tkachov PR target/70830 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1267897..22543ab 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13567,17 +13567,18 @@ ;; movd instead of movq is required to handle broken assemblers. (define_insn "vec_concatv2di" [(set (match_operand:V2DI 0 "register_operand" - "=Yr,*x,x ,Yi,x ,!x,x,x,x,x,x") + "=Yr,*x,x ,v ,Yi,v ,!x,x,v ,x,x,v") (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" - " 0, 0,x ,r ,xm,*y,0,x,0,0,x") + " 0, 0,x ,Yv,r ,vm,*y,0,Yv,0,0,v") (match_operand:DI 2 "vector_move_operand" - "*rm,rm,rm,C ,C ,C ,x,x,x,m,m")))] + "*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))] "TARGET_SSE" "@ pinsrq\t{$1, %2, %0|%0, %2, 1} pinsrq\t{$1, %2, %0|%0, %2, 1} vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1} + vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1} * return HAVE_AS_IX86_INTERUNIT_MOVQ ? \"%vmovq\t{%1, %0|%0, %1}\" : \"%vmovd\t{%1, %0|%0, %1}\"; %vmovq\t{%1, %0|%0, %1} movq2dq\t{%1, %0|%0, %1} @@ -13592,40 +13593,46 @@ (eq_attr "alternative" "2") (const_string "x64_avx") (eq_attr "alternative" "3") + (const_string "x64_avx512dq") + (eq_attr "alternative" "4") (const_string "x64") - (eq_attr "alternative" "4,5") + (eq_attr "alternative" "5,6") (const_string "sse2") - (eq_attr "alternative" "6") + (eq_attr "alternative" "7") (const_string "sse2_noavx") - (eq_attr "alternative" "7,10") + (eq_attr "alternative" "8,11") (const_string "avx") ] (const_string "noavx"))) (set (attr "type") (if_then_else - (eq_attr "alternative" "0,1,2,6,7") + (eq_attr "alternative" "0,1,2,3,7,8") (const_string "sselog") (const_string "ssemov"))) (set (attr "prefix_rex") - (if_then_else (eq_attr "alternative" "0,1,2,3") + (if_then_else (eq_attr "alternative" "0,1,2,3,4") (const_string "1") (const_string "*"))) (set (attr "prefix_extra") - (if_then_else (eq_attr "alternative" "0,1,2") + (if_then_else (eq_attr "alternative" "0,1,2,3") (const_string "1") (const_string "*"))) (set (attr "length_immediate") - (if_then_else (eq_attr "alternative" "0,1,2") + (if_then_else (eq_attr "alternative" "0,1,2,3") (const_string "1") (const_string "*"))) (set (attr "prefix") - (cond [(eq_attr "alternative" "2,7,10") + (cond [(eq_attr "alternative" "2") (const_string "vex") - (eq_attr "alternative" "3,4") + (eq_attr "alternative" "3") + (const_string "evex") + (eq_attr "alternative" "4,5") (const_string "maybe_vex") + (eq_attr "alternative" "8,11") + (const_string "maybe_evex") ] (const_string "orig"))) - (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")]) + (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")]) (define_expand "vec_unpacks_lo_" [(match_operand: 0 "register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6d5ee16..79554ec 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2016-06-02 Jakub Jelinek + + * gcc.target/i386/avx512dq-concatv2di-1.c: New test. + * gcc.target/i386/avx512vl-concatv2di-1.c: New test. + * gcc.target/i386/sse2-init-v2di-2.c: Adjust expected vec_concatv2di + alternative number. + 2016-05-31 Michael Meissner * gcc.target/powerpc/p9-splat-4.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-concatv2di-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-concatv2di-1.c new file mode 100644 index 0000000..82cb402 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-concatv2di-1.c @@ -0,0 +1,78 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512dq -masm=att -mtune=haswell" } */ + +typedef long long V __attribute__((vector_size (16))); + +void +f1 (long long x, long long y) +{ + register long long a __asm ("xmm16"); + register V c __asm ("xmm17"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, y }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vpinsrq\[^\n\r]*\\\$1\[^\n\r]*%rsi\[^\n\r]*%xmm16\[^\n\r]*%xmm17" } } */ + +void +f2 (long long x, long long *y) +{ + register long long a __asm ("xmm18"); + register V c __asm ("xmm19"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, *y }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vpinsrq\[^\n\r]*\\\$1\[^\n\r]*%\[re]si\[^\n\r]*%xmm18\[^\n\r]*%xmm19" } } */ + +void +f3 (long long x) +{ + register V a __asm ("xmm20"); + a = (V) { x, 0 }; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vmov\[dq]\[^\n\r]*%rdi\[^\n\r]*%xmm20" } } */ + +void +f4 (long long *x) +{ + register V a __asm ("xmm21"); + a = (V) { *x, 0 }; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vmovq\[^\n\r]*%\[re]di\[^\n\r]*%xmm21" } } */ + +void +f5 (long long x) +{ + register long long a __asm ("xmm22"); + register V c __asm ("xmm23"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, 0 }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vmovq\[^\n\r]*%xmm22\[^\n\r]*%xmm23" } } */ + +void +f6 (long long x, long long y) +{ + register long long a __asm ("xmm24"); + register long long b __asm ("xmm25"); + register V c __asm ("xmm26"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + c = (V) { a, b }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vpunpcklqdq\[^\n\r]*%xmm25\[^\n\r]*%xmm24\[^\n\r]*%xmm26" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-concatv2di-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-concatv2di-1.c new file mode 100644 index 0000000..8e63707 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-concatv2di-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512dq -masm=att -mtune=haswell" } */ + +typedef long long V __attribute__((vector_size (16))); + +void +f1 (long long x, long long y) +{ + register long long a __asm ("xmm16"); + register V c __asm ("xmm17"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, y }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler-not "vpinsrq\[^\n\r]*\[^\n\r]*%xmm1\[6-9]" } } */ +/* { dg-final { scan-assembler-not "vpinsrq\[^\n\r]*\[^\n\r]*%xmm\[23]\[0-9]" } } */ + +void +f2 (long long x, long long *y) +{ + register long long a __asm ("xmm18"); + register V c __asm ("xmm19"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, *y }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vmovhps\[^\n\r]*%\[re]si\[^\n\r]*%xmm18\[^\n\r]*%xmm19" } } */ + +void +f3 (long long x) +{ + register V a __asm ("xmm20"); + a = (V) { x, 0 }; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vmov\[dq]\[^\n\r]*%rdi\[^\n\r]*%xmm20" } } */ + +void +f4 (long long *x) +{ + register V a __asm ("xmm21"); + a = (V) { *x, 0 }; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vmovq\[^\n\r]*%\[re]di\[^\n\r]*%xmm21" } } */ + +void +f5 (long long x) +{ + register long long a __asm ("xmm22"); + register V c __asm ("xmm23"); + a = x; + asm volatile ("" : "+v" (a)); + c = (V) { a, 0 }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vmovq\[^\n\r]*%xmm22\[^\n\r]*%xmm23" } } */ + +void +f6 (long long x, long long y) +{ + register long long a __asm ("xmm24"); + register long long b __asm ("xmm25"); + register V c __asm ("xmm26"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + c = (V) { a, b }; + asm volatile ("" : "+v" (c)); +} + +/* { dg-final { scan-assembler "vpunpcklqdq\[^\n\r]*%xmm25\[^\n\r]*%xmm24\[^\n\r]*%xmm26" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c index 97d0441..38ca217 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c +++ b/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c @@ -10,4 +10,4 @@ test (long long b) return _mm_cvtsi64_si128 (b); } -/* { dg-final { scan-assembler-times "vec_concatv2di/4" 1 } } */ +/* { dg-final { scan-assembler-times "vec_concatv2di/5" 1 } } */